Lines Matching +full:reg +full:- +full:io +full:- +full:width
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/nrf-saadc.h>
10 #include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h>
11 #include <zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h>
12 #include <zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h>
13 #include <zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h>
15 /delete-node/ &sw_pwm;
18 #address-cells = <1>;
19 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
26 compatible = "arm,cortex-m33";
27 reg = <2>;
29 clock-frequency = <DT_FREQ_M(320)>;
33 compatible = "arm,cortex-m33";
34 reg = <3>;
36 clock-frequency = <DT_FREQ_M(256)>;
41 reg = <13>;
43 clock-frequency = <DT_FREQ_M(16)>;
45 nordic,bus-width = <32>;
48 compatible = "nordic,nrf-vevif-task-rx";
50 interrupt-parent = <&cpuppr_clic>;
67 #mbox-cells = <1>;
69 nordic,tasks-mask = <0x0000fff0>;
74 reserved-memory {
75 #address-cells = <1>;
76 #size-cells = <1>;
79 reg = <0xe6b7000 DT_SIZE_K(40)>;
85 compatible = "fixed-clock";
86 #clock-cells = <0>;
87 clock-frequency = <DT_FREQ_M(32)>;
91 compatible = "fixed-clock";
92 #clock-cells = <0>;
93 clock-frequency = <DT_FREQ_M(16)>;
98 #address-cells = <1>;
99 #size-cells = <1>;
103 reg = <0xe000000 DT_SIZE_K(8192)>;
104 erase-block-size = <4096>;
105 write-block-size = <16>;
109 compatible = "nordic,nrf-uicr-v2";
110 reg = <0xfff8000 DT_SIZE_K(2)>;
115 compatible = "nordic,nrf-uicr-v2";
116 reg = <0xfffa000 DT_SIZE_K(2)>;
121 compatible = "nordic,nrf-ficr";
122 reg = <0xfffe000 DT_SIZE_K(2)>;
123 #nordic,ficr-cells = <1>;
127 compatible = "mmio-sram";
128 reg = <0x22000000 DT_SIZE_K(32)>;
129 #address-cells = <1>;
130 #size-cells = <1>;
135 compatible = "mmio-sram";
136 reg = <0x23000000 DT_SIZE_K(192)>;
137 #address-cells = <1>;
138 #size-cells = <1>;
143 compatible = "mmio-sram";
144 reg = <0x23040000 DT_SIZE_K(32)>;
145 #address-cells = <1>;
146 #size-cells = <1>;
151 #address-cells = <1>;
152 #size-cells = <1>;
156 compatible = "nordic,nrf-hsfll-local";
157 #clock-cells = <0>;
158 reg = <0xd000 0x1000>;
160 clock-frequency = <DT_FREQ_M(320)>;
165 nordic,ficr-names = "vsup", "coarse", "fine";
169 compatible = "nordic,nrf-ipct-local";
170 reg = <0x13000 0x1000>;
178 compatible = "nordic,nrf-wdt";
179 reg = <0x14000 0x1000>;
185 compatible = "nordic,nrf-wdt";
186 reg = <0x15000 0x1000>;
192 compatible = "nordic,nrf-ieee802154";
197 compatible = "nordic,nrf-resetinfo";
198 reg = <0x1e000 0x1000>;
203 #address-cells = <1>;
204 #size-cells = <1>;
208 compatible = "nordic,nrf-hsfll-local";
209 #clock-cells = <0>;
210 reg = <0xd000 0x1000>;
212 clock-frequency = <DT_FREQ_M(256)>;
217 nordic,ficr-names = "vsup", "coarse", "fine";
221 compatible = "nordic,nrf-wdt";
222 reg = <0x13000 0x1000>;
228 compatible = "nordic,nrf-wdt";
229 reg = <0x14000 0x1000>;
235 compatible = "nordic,nrf-resetinfo";
236 reg = <0x1e000 0x1000>;
240 compatible = "nordic,nrf-dppic-local";
241 reg = <0x22000 0x1000>;
246 compatible = "nordic,nrf-ipct-local";
247 reg = <0x24000 0x1000>;
255 compatible = "nordic,nrf-egu";
256 reg = <0x25000 0x1000>;
262 compatible = "nordic,nrf-timer";
263 reg = <0x28000 0x1000>;
265 cc-num = <8>;
267 max-bit-width = <32>;
268 max-frequency = <DT_FREQ_M(32)>;
273 compatible = "nordic,nrf-timer";
274 reg = <0x29000 0x1000>;
276 cc-num = <8>;
278 max-bit-width = <32>;
279 max-frequency = <DT_FREQ_M(32)>;
284 compatible = "nordic,nrf-timer";
285 reg = <0x2a000 0x1000>;
287 cc-num = <8>;
289 max-bit-width = <32>;
290 max-frequency = <DT_FREQ_M(32)>;
295 compatible = "nordic,nrf-rtc";
296 reg = <0x2b000 0x1000>;
298 cc-num = <4>;
299 clock-frequency = <32768>;
305 compatible = "nordic,nrf-radio";
306 reg = <0x2c000 0x1000>;
308 ble-2mbps-supported;
309 ble-coded-phy-supported;
310 dfe-supported;
311 ieee802154-supported;
315 compatible = "nordic,nrf-ieee802154";
321 compatible = "nordic,nrf-ccm";
322 reg = <0x3a000 0x1000>;
328 compatible = "nordic,nrf-ecb";
329 reg = <0x3b000 0x1000>;
335 compatible = "nordic,nrf-ccm";
336 reg = <0x3c000 0x1000>;
342 compatible = "nordic,nrf-ecb";
343 reg = <0x3d000 0x1000>;
350 #address-cells = <1>;
351 #size-cells = <1>;
355 compatible = "nordic,nrf-usbhs", "snps,dwc2";
356 reg = <0x86000 0x1000>, <0x2f700000 0x40000>;
357 reg-names = "wrapper", "core";
359 num-in-eps = <8>;
360 num-out-eps = <10>;
368 compatible = "nordic,nrf-exmif";
369 #address-cells = <1>;
370 #size-cells = <0>;
371 reg = <0x95000 0x500 0x95500 0xb00>;
372 reg-names = "wrapper", "core";
374 clock-frequency = <DT_FREQ_M(400)>;
375 fifo-depth = <32>;
376 max-xfer-size = <16>;
381 reg = <0x99000 0x1000>;
383 #mbox-cells = <1>;
387 reg = <0x9a000 0x1000>;
389 #mbox-cells = <1>;
393 reg = <0x9b000 0x1000>;
395 #mbox-cells = <1>;
399 reg = <0x9c000 0x1000>;
401 #mbox-cells = <1>;
404 canpll: clock-controller@8c2000{
405 compatible = "nordic,nrf-auxpll";
406 reg = <0x8c2000 0x1000>;
409 #clock-cells = <0>;
412 nordic,out-div = <2>;
413 nordic,out-drive = <0>;
414 nordic,current-tune = <6>;
415 nordic,sdm-disable;
421 compatible = "nordic,nrf-vevif-task-tx";
422 reg = <0x8c8000 0x1000>;
424 #mbox-cells = <1>;
426 nordic,tasks-mask = <0xfffff0ff>;
430 compatible = "nordic,nrf-ipct-global";
431 reg = <0x8d1000 0x1000>;
434 global-domain-id = <12>;
438 compatible = "nordic,nrf-can";
439 reg = <0x8d8000 0x400>, <0x2fbef800 0x800>, <0x2fbe8000 0x7800>;
440 reg-names = "wrapper", "m_can", "message_ram";
443 bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
448 compatible = "nordic,nrf-can";
449 reg = <0x8db000 0x400>, <0x2fbf7800 0x800>, <0x2fbf0000 0x7800>;
450 reg-names = "wrapper", "m_can", "message_ram";
453 bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
458 compatible = "nordic,nrf-dppic-global";
459 reg = <0x8e1000 0x1000>;
464 compatible = "nordic,nrf-timer";
465 reg = <0x8e2000 0x1000>;
467 cc-num = <6>;
469 max-bit-width = <32>;
470 max-frequency = <DT_FREQ_M(320)>;
475 compatible = "nordic,nrf-timer";
476 reg = <0x8e3000 0x1000>;
478 cc-num = <6>;
480 max-bit-width = <32>;
481 max-frequency = <DT_FREQ_M(320)>;
486 compatible = "nordic,nrf-pwm";
487 reg = <0x8e4000 0x1000>;
490 #pwm-cells = <3>;
494 compatible = "nordic,nrf-spim";
495 reg = <0x8e6000 0x1000>;
497 easydma-maxcnt-bits = <15>;
499 max-frequency = <DT_FREQ_M(32)>;
500 #address-cells = <1>;
501 #size-cells = <0>;
502 rx-delay-supported;
503 rx-delay = <1>;
504 nordic,clockpin-enable = <NRF_FUN_SPIM_SCK>,
509 compatible = "nordic,nrf-uarte";
510 reg = <0x8e6000 0x1000>;
513 endtx-stoptx-supported;
514 frame-timeout-supported;
518 compatible = "nordic,nrf-spim";
519 reg = <0x8e7000 0x1000>;
521 easydma-maxcnt-bits = <15>;
523 max-frequency = <DT_FREQ_M(32)>;
524 #address-cells = <1>;
525 #size-cells = <0>;
526 rx-delay-supported;
527 rx-delay = <1>;
528 nordic,clockpin-enable = <NRF_FUN_SPIM_SCK>,
533 compatible = "nordic,nrf-vpr-coprocessor";
534 reg = <0x908000 0x1000>;
536 #address-cells = <1>;
537 #size-cells = <1>;
541 compatible = "nordic,nrf-vevif-task-tx";
542 reg = <0x0 0x1000>;
544 #mbox-cells = <1>;
546 nordic,tasks-mask = <0x0000fff0>;
551 compatible = "nordic,nrf-ipct-global";
552 reg = <0x921000 0x1000>;
555 global-domain-id = <13>;
559 compatible = "nordic,nrf-dppic-global";
560 reg = <0x922000 0x1000>;
565 compatible = "nordic,nrf-rtc";
566 reg = <0x928000 0x1000>;
568 cc-num = <4>;
569 clock-frequency = <32768>;
575 compatible = "nordic,nrf-rtc";
576 reg = <0x929000 0x1000>;
578 cc-num = <4>;
579 clock-frequency = <32768>;
585 compatible = "nordic,nrf-wdt";
586 reg = <0x92b000 0x1000>;
592 compatible = "nordic,nrf-wdt";
593 reg = <0x92c000 0x1000>;
599 compatible = "nordic,nrf-gpiote";
600 reg = <0x934000 0x1000>;
606 compatible = "nordic,nrf-gpiote";
607 reg = <0x935000 0x1000>;
613 compatible = "nordic,nrf-gpio";
614 reg = <0x938000 0x200>;
616 #gpio-cells = <2>;
617 gpio-controller;
618 gpiote-instance = <&gpiote130>;
624 compatible = "nordic,nrf-gpio";
625 reg = <0x938200 0x200>;
627 #gpio-cells = <2>;
628 gpio-controller;
629 gpiote-instance = <&gpiote130>;
635 compatible = "nordic,nrf-gpio";
636 reg = <0x938400 0x200>;
638 #gpio-cells = <2>;
639 gpio-controller;
640 gpiote-instance = <&gpiote130>;
646 compatible = "nordic,nrf-gpio";
647 reg = <0x938c00 0x200>;
649 #gpio-cells = <2>;
650 gpio-controller;
656 compatible = "nordic,nrf-gpio";
657 reg = <0x939000 0x200>;
659 #gpio-cells = <2>;
660 gpio-controller;
666 compatible = "nordic,nrf-gpio";
667 reg = <0x939200 0x200>;
669 #gpio-cells = <2>;
670 gpio-controller;
671 gpiote-instance = <&gpiote130>;
677 compatible = "nordic,nrf-gpio";
678 reg = <0x939600 0x200>;
680 #gpio-cells = <2>;
681 gpio-controller;
682 gpiote-instance = <&gpiote131>;
688 compatible = "nordic,nrf-dppic-global";
689 reg = <0x981000 0x1000>;
694 compatible = "nordic,nrf-saadc";
695 reg = <0x982000 0x1000>;
698 #io-channel-cells = <1>;
703 * Use compatible "nordic,nrf-comp" to configure as COMP
704 * Use compatible "nordic,nrf-lpcomp" to configure as LPCOMP
706 compatible = "nordic,nrf-comp";
707 reg = <0x983000 0x1000>;
712 temp: temperature-sensor@984000 {
713 compatible = "nordic,nrf-temp";
714 reg = <0x984000 0x1000>;
720 compatible = "nordic,nrf-dppic-global";
721 reg = <0x991000 0x1000>;
726 compatible = "nordic,nrf-qdec";
727 reg = <0x994000 0x1000>;
733 compatible = "nordic,nrf-qdec";
734 reg = <0x995000 0x1000>;
740 compatible = "nordic,nrf-grtc";
741 reg = <0x99c000 0x1000>;
743 cc-num = <16>;
747 compatible = "nordic,nrf-dppic-global";
748 reg = <0x9a1000 0x1000>;
753 compatible = "nordic,nrf-timer";
754 reg = <0x9a2000 0x1000>;
756 cc-num = <6>;
758 max-bit-width = <32>;
763 compatible = "nordic,nrf-timer";
764 reg = <0x9a3000 0x1000>;
766 cc-num = <6>;
768 max-bit-width = <32>;
773 compatible = "nordic,nrf-pwm";
774 reg = <0x9a4000 0x1000>;
777 #pwm-cells = <3>;
781 compatible = "nordic,nrf-twim";
782 reg = <0x9a5000 0x1000>;
785 easydma-maxcnt-bits = <15>;
786 #address-cells = <1>;
787 #size-cells = <0>;
788 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
790 zephyr,pm-device-runtime-auto;
794 compatible = "nordic,nrf-spim";
795 reg = <0x9a5000 0x1000>;
797 easydma-maxcnt-bits = <15>;
799 max-frequency = <DT_FREQ_M(8)>;
800 #address-cells = <1>;
801 #size-cells = <0>;
802 rx-delay-supported;
803 rx-delay = <1>;
804 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
811 compatible = "nordic,nrf-uarte";
812 reg = <0x9a5000 0x1000>;
815 nordic,clockpin-enable = <NRF_FUN_UART_TX>;
816 endtx-stoptx-supported;
817 frame-timeout-supported;
821 compatible = "nordic,nrf-twim";
822 reg = <0x9a6000 0x1000>;
825 easydma-maxcnt-bits = <15>;
826 #address-cells = <1>;
827 #size-cells = <0>;
828 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
830 zephyr,pm-device-runtime-auto;
834 compatible = "nordic,nrf-spim";
835 reg = <0x9a6000 0x1000>;
837 easydma-maxcnt-bits = <15>;
839 max-frequency = <DT_FREQ_M(8)>;
840 #address-cells = <1>;
841 #size-cells = <0>;
842 rx-delay-supported;
843 rx-delay = <1>;
844 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
851 compatible = "nordic,nrf-uarte";
852 reg = <0x9a6000 0x1000>;
855 nordic,clockpin-enable = <NRF_FUN_UART_TX>;
856 endtx-stoptx-supported;
857 frame-timeout-supported;
861 compatible = "nordic,nrf-dppic-global";
862 reg = <0x9b1000 0x1000>;
867 compatible = "nordic,nrf-timer";
868 reg = <0x9b2000 0x1000>;
870 cc-num = <6>;
872 max-bit-width = <32>;
877 compatible = "nordic,nrf-timer";
878 reg = <0x9b3000 0x1000>;
880 cc-num = <6>;
882 max-bit-width = <32>;
887 compatible = "nordic,nrf-pwm";
888 reg = <0x9b4000 0x1000>;
891 #pwm-cells = <3>;
895 compatible = "nordic,nrf-twim";
896 reg = <0x9b5000 0x1000>;
899 easydma-maxcnt-bits = <15>;
900 #address-cells = <1>;
901 #size-cells = <0>;
902 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
904 zephyr,pm-device-runtime-auto;
908 compatible = "nordic,nrf-spim";
909 reg = <0x9b5000 0x1000>;
911 easydma-maxcnt-bits = <15>;
913 max-frequency = <DT_FREQ_M(8)>;
914 #address-cells = <1>;
915 #size-cells = <0>;
916 rx-delay-supported;
917 rx-delay = <1>;
918 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
925 compatible = "nordic,nrf-uarte";
926 reg = <0x9b5000 0x1000>;
929 nordic,clockpin-enable = <NRF_FUN_UART_TX>;
930 endtx-stoptx-supported;
931 frame-timeout-supported;
935 compatible = "nordic,nrf-twim";
936 reg = <0x9b6000 0x1000>;
939 easydma-maxcnt-bits = <15>;
940 #address-cells = <1>;
941 #size-cells = <0>;
942 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
944 zephyr,pm-device-runtime-auto;
948 compatible = "nordic,nrf-spim";
949 reg = <0x9b6000 0x1000>;
951 easydma-maxcnt-bits = <15>;
953 max-frequency = <DT_FREQ_M(8)>;
954 #address-cells = <1>;
955 #size-cells = <0>;
956 rx-delay-supported;
957 rx-delay = <1>;
958 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
965 compatible = "nordic,nrf-uarte";
966 reg = <0x9b6000 0x1000>;
969 nordic,clockpin-enable = <NRF_FUN_UART_TX>;
970 endtx-stoptx-supported;
971 frame-timeout-supported;
975 compatible = "nordic,nrf-dppic-global";
976 reg = <0x9c1000 0x1000>;
981 compatible = "nordic,nrf-timer";
982 reg = <0x9c2000 0x1000>;
984 cc-num = <6>;
986 max-bit-width = <32>;
991 compatible = "nordic,nrf-timer";
992 reg = <0x9c3000 0x1000>;
994 cc-num = <6>;
996 max-bit-width = <32>;
1001 compatible = "nordic,nrf-pwm";
1002 reg = <0x9c4000 0x1000>;
1005 #pwm-cells = <3>;
1009 compatible = "nordic,nrf-twim";
1010 reg = <0x9c5000 0x1000>;
1013 easydma-maxcnt-bits = <15>;
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1016 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
1018 zephyr,pm-device-runtime-auto;
1022 compatible = "nordic,nrf-spim";
1023 reg = <0x9c5000 0x1000>;
1025 easydma-maxcnt-bits = <15>;
1027 max-frequency = <DT_FREQ_M(8)>;
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1030 rx-delay-supported;
1031 rx-delay = <1>;
1032 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
1039 compatible = "nordic,nrf-uarte";
1040 reg = <0x9c5000 0x1000>;
1043 nordic,clockpin-enable = <NRF_FUN_UART_TX>;
1044 endtx-stoptx-supported;
1045 frame-timeout-supported;
1049 compatible = "nordic,nrf-twim";
1050 reg = <0x9c6000 0x1000>;
1053 easydma-maxcnt-bits = <15>;
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1056 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
1058 zephyr,pm-device-runtime-auto;
1062 compatible = "nordic,nrf-spim";
1063 reg = <0x9c6000 0x1000>;
1065 easydma-maxcnt-bits = <15>;
1067 max-frequency = <DT_FREQ_M(8)>;
1068 #address-cells = <1>;
1069 #size-cells = <0>;
1070 rx-delay-supported;
1071 rx-delay = <1>;
1072 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
1079 compatible = "nordic,nrf-uarte";
1080 reg = <0x9c6000 0x1000>;
1083 nordic,clockpin-enable = <NRF_FUN_UART_TX>;
1084 endtx-stoptx-supported;
1085 frame-timeout-supported;
1089 compatible = "nordic,nrf-dppic-global";
1090 reg = <0x9d1000 0x1000>;
1095 compatible = "nordic,nrf-timer";
1096 reg = <0x9d2000 0x1000>;
1098 cc-num = <6>;
1100 max-bit-width = <32>;
1105 compatible = "nordic,nrf-timer";
1106 reg = <0x9d3000 0x1000>;
1108 cc-num = <6>;
1110 max-bit-width = <32>;
1115 compatible = "nordic,nrf-pwm";
1116 reg = <0x9d4000 0x1000>;
1119 #pwm-cells = <3>;
1123 compatible = "nordic,nrf-twim";
1124 reg = <0x9d5000 0x1000>;
1127 easydma-maxcnt-bits = <15>;
1128 #address-cells = <1>;
1129 #size-cells = <0>;
1130 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
1132 zephyr,pm-device-runtime-auto;
1136 compatible = "nordic,nrf-spim";
1137 reg = <0x9d5000 0x1000>;
1139 easydma-maxcnt-bits = <15>;
1141 max-frequency = <DT_FREQ_M(8)>;
1142 #address-cells = <1>;
1143 #size-cells = <0>;
1144 rx-delay-supported;
1145 rx-delay = <1>;
1146 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
1153 compatible = "nordic,nrf-uarte";
1154 reg = <0x9d5000 0x1000>;
1157 nordic,clockpin-enable = <NRF_FUN_UART_TX>;
1158 endtx-stoptx-supported;
1159 frame-timeout-supported;
1163 compatible = "nordic,nrf-twim";
1164 reg = <0x9d6000 0x1000>;
1167 easydma-maxcnt-bits = <15>;
1168 #address-cells = <1>;
1169 #size-cells = <0>;
1170 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
1172 zephyr,pm-device-runtime-auto;
1176 compatible = "nordic,nrf-spim";
1177 reg = <0x9d6000 0x1000>;
1179 easydma-maxcnt-bits = <15>;
1181 max-frequency = <DT_FREQ_M(8)>;
1182 #address-cells = <1>;
1183 #size-cells = <0>;
1184 rx-delay-supported;
1185 rx-delay = <1>;
1186 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
1193 compatible = "nordic,nrf-uarte";
1194 reg = <0x9d6000 0x1000>;
1197 nordic,clockpin-enable = <NRF_FUN_UART_TX>;
1198 endtx-stoptx-supported;
1199 frame-timeout-supported;
1204 cpuapp_ppb: cpuapp-ppb-bus {
1205 #address-cells = <1>;
1206 #size-cells = <1>;
1209 compatible = "arm,armv8m-systick";
1210 reg = <0xe000e010 0x10>;
1214 cpuapp_nvic: interrupt-controller@e000e100 {
1215 compatible = "arm,v8m-nvic";
1216 reg = <0xe000e100 0xc00>;
1217 arm,num-irq-priority-bits = <3>;
1218 #interrupt-cells = <2>;
1219 interrupt-controller;
1220 #address-cells = <1>;
1224 cpurad_ppb: cpurad-ppb-bus {
1225 #address-cells = <1>;
1226 #size-cells = <1>;
1229 compatible = "arm,armv8m-systick";
1230 reg = <0xe000e010 0x10>;
1234 cpurad_nvic: interrupt-controller@e000e100 {
1235 compatible = "arm,v8m-nvic";
1236 reg = <0xe000e100 0xc00>;
1237 arm,num-irq-priority-bits = <3>;
1238 #interrupt-cells = <2>;
1239 interrupt-controller;
1240 #address-cells = <1>;
1244 cpuppr_private: cpuppr-private-bus {
1245 #address-cells = <1>;
1246 #size-cells = <1>;
1248 cpuppr_clic: interrupt-controller@5f909000 {
1249 compatible = "nordic,nrf-clic";
1250 reg = <0x5f909000 0x3000>;
1252 #interrupt-cells = <2>;
1253 interrupt-controller;
1254 #address-cells = <1>;
1259 compatible = "nordic,nrf-temp-nrfs";