Lines Matching +full:high +full:- +full:level

2 # SPDX-License-Identifier: Apache-2.0
6     Based on pincfg-node.yaml binding.
22     pins, such as the 'bias-pull-up' property in group 2. Here is a list of
25     - bias-disable: Disable pull-up/down (default behavior, not required).
26     - bias-pull-down: Enable pull-down resistor.
27     - bias-pull-up: Enable pull-up resistor.
28     - drive-push-pull: Output driver is push-pull (default, not required).
29     - drive-open-drain: Output driver is open-drain.
30     - output-high: Set output state high when pin configured.
31     - output-low: Set output state low when pin configured.
34     - drive-strength
35     - slew-rate
39     An example for MEC174x family, include the chip level pinctrl
40     DTSI file in the board level DTS:
42       #include <microchip/mec5/mec1743qlj-a0-pinctrl.dtsi>
45     and want the chip select 0 to be open-drain.
51         pinctrl-0 = < &shd_cs0_n_gpio055
56         pinctrl-names = "default";
60         drive-open-drain;
63 compatible: "microchip,mec5-pinctrl"
71 child-binding:
77     - name: pincfg-node.yaml
78       property-allowlist:
79         - bias-disable
80         - bias-pull-down
81         - bias-pull-up
82         - drive-push-pull
83         - drive-open-drain
84         - low-power-enable
85         - output-disable
86         - output-enable
87         - output-high
88         - output-low
96     slew-rate:
99         - "low-speed"
100         - "high-speed"
102         Pin speed. The default value of slew-rate is the SoC power-on-reset
107     drive-strength:
110         - "1x"
111         - "2x"
112         - "4x"
113         - "6x"
115         Pin output drive strength for PIO and PIO-24 pin types. Default
116         is "1x" for most pins. PIO pins are 2, 4, 8, or 12 mA. PIO-24 pins
120     microchip,output-func-invert: