Lines Matching +full:mx25r +full:- +full:power +full:- +full:mode

3 # SPDX-License-Identifier: Apache-2.0
5 # Common properties used by nodes describing M25P80-compatible SPI NOR
8 # This extends JESD216-defined features with additional functionality
9 # that may be specific to the vendor of a M25P80-compatible device and
17   requires-ulbpr:
23       protection register that initializes to write-protected.  Use this
27   has-dpd:
33       Power-Down mode that is entered by command 0xB9 to reduce power
35       implies that the RDPD (0xAB) Release from Deep Power Down command
37       Electronic Signature; see t-enter-dpd).
39   dpd-wakeup-sequence:
44       Some devices (Macronix MX25R in particular) wake from deep power
48       (1) tDPDD (Delay Time for Release from Deep Power-Down Mode)
49       (2) tCDRP (CSn Toggling Time before Release from Deep Power-Down Mode)
50       (3) tRDP (Recovery Time for Release from Deep Power-Down Mode)
53       used to wake the chip from Deep Power-Down mode.
55   t-enter-dpd:
62       deep power down.
66   t-exit-dpd:
73       deep power down and be ready to receive additional commands.
77   has-lock:
83       Some devices from certain vendors power-up with block protect bits
87       non-volatile bits in the status register that should not be
93   mxicy,mx25r-power-mode:
96       - "low-power"
97       - "high-performance"
99       Select to configure flash to use ultra low power mode or high
100       performance mode (L/H switch). The high performance mode has
101       faster write and erase performance, but use more power than ultra
102       low power mode.
104       Only supported on Macronix MX25R Ultra Low Power series.
106   use-4b-addr-opcodes:
109       Indicates the device uses special 4-byte address opcodes.
110       Instead of switching to 4-byte addressing mode, the device uses
111       special opcodes for 4-byte addressing.
113       Some devices support 4-byte address opcodes for read/write/erase
115       4-byte address opcodes.