Lines Matching +full:can +full:- +full:transceiver +full:- +full:gpio

3 # SPDX-License-Identifier: Apache-2.0
7   implementation by GPIO bit-banging.
9   Schematic using dual-supply bus transceiver and separate dout and dnoe pins
13             |       +-------------+     |
14             +-------|vcca     vccb|-----+
16    clk-gpios -------|a           b|-------------- SWD CLK
18    noe-gpios -------|dir       gnd|-----+
19                     +-------------+     |
26             |       +-------------+     |
27             +-------|vcca     vccb|-----+
29    dio-gpios -------|a           b|------------*- SWD DIO
31             +-------|dir       gnd|-----+      |
32             |       +-------------+     |      |
39             |       +-------------+     |      |
40             +-------|vcca     vccb|-----+      |
42   dout-gpios -------|a           b|------------+
44   dnoe-gpios -------|dir       gnd|-----+
45                     +-------------+     |
51    clk-gpios ------------------------------------ SWD CLK
53    dio-gpios ------------------------------------ SWD DIO
55   Of course, bidirectional bus transceiver between dio and SWD DIO can also be
58 compatible: "zephyr,swdp-gpio"
63   clk-gpios:
64     type: phandle-array
66     description: GPIO pin used for SWCLK output
68   dio-gpios:
69     type: phandle-array
72       GPIO pin used for SWDIO input. This pin is also used for the SWDIO output
75   dout-gpios:
76     type: phandle-array
78       Optional GPIO pin used for SWDIO output.
80   dnoe-gpios:
81     type: phandle-array
83       GPIO pin used to disable the SWDIO output buffer behind optional
84       pin dout-gpios.
86   noe-gpios:
87     type: phandle-array
91   reset-gpios:
92     type: phandle-array
94       Optional GPIO pin used for RESET output.
96   port-write-cycles:
101       GPIO clock may be different from the CPU clock. This can usually be