Lines Matching +full:row +full:- +full:size
2 # SPDX-License-Identifier: Apache-2.0
7 pinctrl-0 = <&sdram_default>;
8 pinctrl-names = "default";
10 auto-refresh-interval = <10>;
11 auto-refresh-count = <8>;
12 precharge-cycle-count = <3>;
13 multiplex-addr-shift = "10-bit";
14 edian-mode = "little-endian";
15 continuous-access;
16 bus-width = "16-bit";
19 renesas,ra-sdram-timing = <RENESAS_RA_SDRAM_TRAS_6CYCLES
28 Note that you will find definitions for the renesas,ra-sdram-control field at
29 dt-bindings/memory-controller/renesas,ra-sdram.h. This file is already included
36 compatible = "zephyr,memory-region", "mmio-sram";
39 zephyr,memory-region = "SDRAM";
42 compatible: "renesas,ra-sdram"
44 include: [base.yaml, pinctrl-device.yaml]
47 "#address-cells":
51 "#size-cells":
55 pinctrl-0:
58 pinctrl-names:
61 auto-refresh-interval:
64 description: Number of auto-refresh-interval.
66 auto-refresh-count:
69 description: Number of auto-refresh-count.
71 precharge-cycle-count:
74 description: Number of precharge-cycle-count.
76 multiplex-addr-shift:
78 default: "10-bit"
80 - "8-bit"
81 - "9-bit"
82 - "10-bit"
83 - "11-bit"
85 Select the size of the shift towards the lower half of the row address in row address/column
88 edian-mode:
90 default: "little-endian"
92 - "little-endian"
93 - "big-endian"
96 continuous-access:
100 bus-width:
102 default: "16-bit"
104 - "16-bit"
105 - "32-bit"
106 - "8-bit"
109 child-binding:
117 renesas,ra-sdram-timing:
123 - TRAS: Row active interval. The effective value from 1 to 7 cycles
124 - TRCD: Row column latency. The effective value from 1 to 4 cycles
125 - TRP: Row precharge interval. The effective value from 1 to 8 cycles
126 - TWR: Write recovery interval. The effective value from 1 to 2 cycles
127 - TCL: Column latency. The effective value from 1 to 3 cycles
128 - TRFC: Auto-Refresh Request Interval Setting.
129 - TREFW: Auto-Refresh Cycle/Self-Refresh Clearing Cycle Count Setting.