Lines Matching +full:smc +full:- +full:cycle +full:- +full:timing

2 # SPDX-License-Identifier: Apache-2.0
5   Atmel Static Memory Controller (SMC).
7   The SMC allows to interface with static-memory mapped external devices such as
10   The SMC is clocked through the Master Clock (MCK) which is controlled by the
13   The SMC controller can have up to 4 children defining the connected external
17   &smc {
19     pinctrl-0 = <&smc_default>;
20     pinctrl-names = "default";
25       atmel,smc-write-mode = "nwe";
26       atmel,smc-read-mode = "nrd";
27       atmel,smc-setup-timing = <1 1 1 1>;
28       atmel,smc-pulse-timing = <6 6 6 6>;
29       atmel,smc-cycle-timing = <7 7>;
33   The above example configures a is66wv51216dbll-55 device. The device is a
36   each MCK cycle will be equivalent to 8ns. Since the memory full cycle is
37   55ns, as per specification, it requires atmel,smc-cycle-timing of at least
38   7 pulses (56ns). The atmel,smc-cycle-timing is composed of three parts:
41   is66wv51216dbll-55 a minimum setup of 5ns (1 cycle) with at least 45ns
43   Note: Since no hold parameter is available at SMC the atmel,smc-cycle-timing
47     cycle-timing (7) = setup (1) + pulse (6) + hold (0)
50     cycle-timing (10) = setup (1) + pulse (6) + hold (3)
56       compatible = "zephyr,memory-region", "mmio-sram";
59       zephyr,memory-region = "SRAM1";
62 compatible: "atmel,sam-smc"
64 include: [base.yaml, pinctrl-device.yaml]
73   "#address-cells":
77   "#size-cells":
81 child-binding:
83     Child device nodes are representing devices connected to the EBI/SMC bus.
90         The device's SMC Chip Select number.
91         Valid range: 0 - 3
93     atmel,smc-write-mode:
103         - "ncs"
104         - "nwe"
106     atmel,smc-read-mode:
114         - "ncs"
115         - "nrd"
117     atmel,smc-setup-timing:
123         where each value is configured in terms of MCK cycles. The SMC
129     atmel,smc-pulse-timing:
139     atmel,smc-cycle-timing:
143         SMC timing configurations in cycles for the total write and read
145         This value describes the entire write/read operation timing which
146         is defined as: cycle = setup + pulse + hold
147         Value has to be greater or equal to setup + pulse timing and
150         Effective value for each element: 256 x cycle[8:7] + cycle[6:0]