Lines Matching full:smc
5 Atmel Static Memory Controller (SMC).
7 The SMC allows to interface with static-memory mapped external devices such as
10 The SMC is clocked through the Master Clock (MCK) which is controlled by the
13 The SMC controller can have up to 4 children defining the connected external
17 &smc {
25 atmel,smc-write-mode = "nwe";
26 atmel,smc-read-mode = "nrd";
27 atmel,smc-setup-timing = <1 1 1 1>;
28 atmel,smc-pulse-timing = <6 6 6 6>;
29 atmel,smc-cycle-timing = <7 7>;
37 55ns, as per specification, it requires atmel,smc-cycle-timing of at least
38 7 pulses (56ns). The atmel,smc-cycle-timing is composed of three parts:
43 Note: Since no hold parameter is available at SMC the atmel,smc-cycle-timing
62 compatible: "atmel,sam-smc"
83 Child device nodes are representing devices connected to the EBI/SMC bus.
90 The device's SMC Chip Select number.
93 atmel,smc-write-mode:
106 atmel,smc-read-mode:
117 atmel,smc-setup-timing:
123 where each value is configured in terms of MCK cycles. The SMC
129 atmel,smc-pulse-timing:
139 atmel,smc-cycle-timing:
143 SMC timing configurations in cycles for the total write and read