Lines Matching full:is
10 The SMC is clocked through the Master Clock (MCK) which is controlled by the
14 memory devices. The reg property is set to the device's Chip Select.
33 The above example configures a is66wv51216dbll-55 device. The device is a
35 and OE inputs respectively. Assuming that MCK is 120MHz (cpu at full speed)
36 each MCK cycle will be equivalent to 8ns. Since the memory full cycle is
38 7 pulses (56ns). The atmel,smc-cycle-timing is composed of three parts:
39 setup, pulse and hold. The setup is used to address the memory. The pulse
40 is the time used to read/write. The hold is used to release memory. For the
42 (6 cycles) for CPU read/write and no hold time is required.
43 Note: Since no hold parameter is available at SMC the atmel,smc-cycle-timing
97 Select which signal is used for the write operation, either the chip
98 select (ncs) or a dedicated write enable pin (nwe). The data is put
110 Select which signal is used for the read operation, either the chip
111 select (ncs) or a dedicated output enable pin (nrd). The data is read
121 This value is used to setup memory region (set address). The setup
122 values is an array of the signals NWE, NCS_WR, NRD and NCS_RD
123 where each value is configured in terms of MCK cycles. The SMC
125 consecutive reads/writes are used. Each value is encoded in
127 The effective value for each element is: 128 x setup[5] + setup[4:0]
133 This value is used to effectivelly read/write at memory region (pulse phase).
134 The pulse value is an array of the signals NWE, NCS_WR, NRD and NCS_RD where
135 each value is configured in terms of MCK cycles and a value of 0 is forbidden.
136 Each value is encoded in 7 bits where the highest bit adds an offset of 256
137 cycles. The effective value for each element is: 256 x setup[6] + setup[5:0]
146 is defined as: cycle = setup + pulse + hold
148 is encoded in 9 bits where the two highest bits are multiplied