Lines Matching +full:tx +full:- +full:threshold +full:- +full:ctrl
2 # SPDX - License - Identifier : Apache - 2.0
9 - name: reset-device.yaml
10 - name: ethernet-controller.yaml
17 max-frame-size:
23 means that normally xgmac will reject any frame above max-frame-size
27 max-speed:
30 - 10
31 - 100
32 - 1000
33 - 2500
40 soft PCS is connected to XGMAC through GMII. make sure the phy-connection-type is
42 tx-fifo-size:
45 - 1024
46 - 2048
47 - 4096
48 - 8192
49 - 16384
50 - 32768
51 - 65536
52 - 131072
53 - 262144
57 rx-fifo-size:
60 - 1024
61 - 2048
62 - 4096
63 - 8192
64 - 16384
65 - 32768
66 - 65536
67 - 131072
68 - 262144
72 num-dma-ch:
77 num-tx-queues:
81 Number of hardware TX queues range: 1 to 8.
82 num-rx-queues:
87 num-tc:
92 full-duplex-mode-en:
97 wr-osr-lmt:
104 rd-osr-lmt:
116 edma-tdps:
120 Tx Descriptor Pre-fetch threshold Size.
121 This field controls the threshold in the Descriptor cache after
122 which the DMA starts pre-fetching the TxDMA descriptors. The
126 the programmed threshold (each descriptor is 16 bytes)
128 edma-rdps:
132 Rx Descriptor Pre-fetch threshold Size.
133 This field controls the threshold in the Descriptor cache after
134 which the DMA starts pre-fetching the RxDMA descriptors. The
138 the programmed threshold (each descriptor is 16 bytes)
208 Address-Aligned Beats.
209 When this is enabled, the AXI master performs address-aligned
215 DMA master enables the enhanced address mode (40-bit or 48-bit addressing mode).
216 In this mode, the DMA engine uses either the 40-bit or 48-bit address, depending
218 dma-ch-mss:
226 dma-ch-tdrl:
231 This field sets the maximum number of Tx descriptors in the
234 dma-ch-rdrl:
242 dma-ch-rbsz:
252 dma-ch-arbs:
258 to a non-zero value (when split header(SPH) feature is not enabled).
261 limited to 1016 or 1008-bytes depending on the data bus
262 widths (64-bit or 128-bit respectively). When ARBS=0, Rx
264 ARBS field is 7 or 6-bits depending on the data bus widths
265 (64-bit or 128-bit respectively).
266 dma-ch-rxpbl:
273 dma-ch-txpbl:
280 dma-ch-sph:
283 Header-Payload Split.
291 dma-ch-edse:
297 dma-ch-tse:
303 for those packets for which the TSE is set in the Tx Normal
305 dma-ch-osp:
312 mtl-raa:
318 mtl-etsalg:
329 rxq-dyn-dma-en:
335 rxq-dma-ch-sel:
336 type: uint8-array
340 effect when rxQ-DynDma-En is enabled.
341 range 0 - 7
342 txq-size:
343 type: uint8-array
347 in blocks of 256 bytes. = (txQ-size + 1) x 256
348 range: 0 - 7
349 map-queue-tc:
350 type: uint8-array
353 Queue to Traffic Class Mapping. range 0 - 7
354 tx-threshold-ctrl:
355 type: uint8-array
358 Transmit Threshold Control.
359 These field control the threshold level of the MTL Tx Queue.
360 Transmission starts when the packet size within the MTL Tx
361 Queue is larger than the threshold. In addition, full packets
362 with length less than the threshold are also transmitted. This
364 range 0 - 7
373 rx-threshold-ctrl:
374 type: uint8-array
379 the threshold. In addition, full packets with length less than the
380 threshold are automatically transferred. The value of 11 is not
384 range 0 - 3
389 rxq-size:
390 type: uint8-array
394 Receive queues in blocks 256 bytes. = (rxQ-size + 1) x 256
395 Range: 0 - 127 ,
396 tx-store-fwrd-en:
401 starts when a full packet resides in the MTL Tx Queue.
403 hfc-en:
408 signal operation, based on the fill-level of Rx queue, is enabled.
410 cs-error-pkt-drop-dis:
416 rx-store-fwrd-en:
423 fep-en:
430 fup-en:
437 priorities-map-tc:
445 range: 0 - 7 and max array size is 8
447 tx-sel-algorithm:
448 type: uint8-array
453 range: 0 -strict priority
454 1 - Credit based shaper
455 2 - Enhanced Transmission Selection
456 jumbo-pkt-en:
463 gaint-pkt-size-limit: