Lines Matching +full:16 +full:- +full:128
2 # SPDX-License-Identifier: Apache-2.0
10 an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
27 compatible: "st,stm32u5-pll-clock"
29 include: [clock-controller.yaml, base.yaml]
33 "#clock-cells":
39 div-m:
45 Valid range: 1 - 16
47 mul-n:
52 Valid range: 4 - 512
54 div-p:
58 Valid range: 1 - 128
60 div-q:
64 Valid range: 1 - 128
66 div-r:
73 Valid range: 1 - 128
79 Valid range: 0 - 8191