Lines Matching +full:div +full:- +full:q

2 # SPDX-License-Identifier: Apache-2.0
14     f(PLL_P) = f(VCO clock) / PLLP  --> to ADC
15     f(PLL_Q) = f(VCO clock) / PLLQ  --> to RNG
16     f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)
22 compatible: "st,stm32u0-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
27   "#clock-cells":
33   div-m:
39         Valid range: 1 - 8
41   mul-n:
46         Valid range: 4 - 127
48   div-p:
52         Valid range: 2 - 32
54   div-q:
57         PLL VCO division factor Q
58         Valid range: 2 - 8
60   div-r:
65         Valid range: 2 - 8