Lines Matching full:pll
5 PLL node binding for STM32L4 and STM32L5 devices
7 It can be used to describe 3 different PLLs: PLL, PLLSAI1 and PLLSAI2.
8 Only main PLL is supported for now.
14 Each PLL can have up to 3 output clocks and for each output clock, the
21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
23 The PLL output frequency must not exceed 80 MHz.
25 compatible: "st,stm32l4-pll-clock"
40 Division factor for the main PLL and audio PLLs (PLLSAI1 and PLLSAI2)
48 Main PLL multiplication factor for VCO
54 Main PLL division factor for PLLSAI3CLK
62 Main PLL division factor for PLL48M1CLK (48 MHz clock).
73 Main PLL division factor for PLLCLK (system clock)