Lines Matching full:clock

10   These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
12   clock in this acceptable range.
14   Each PLL can have up to 3 output clocks and for each output clock, the
17     f(PLL_P) = f(VCO clock) / PLLP  --> PLLSAI3CLK
18     f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48M1CLK
19     f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)
21       with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
25 compatible: "st,stm32l4-pll-clock"
27 include: [clock-controller.yaml, base.yaml]
30   "#clock-cells":
41         input clock
62         Main PLL division factor for PLL48M1CLK (48 MHz clock).
73         Main PLL division factor for PLLCLK (system clock)