Lines Matching +full:div +full:- +full:t

2 # SPDX-License-Identifier: Apache-2.0
16     f(PLL_Px) = f(VCOx clock) / PLLPx   -> pllx_p_ck ((pll1_p_ck : sys_ck))
17     f(PLL_Qx) = f(VCOx clock) / PLLQx   -> pllx_q_ck
18     f(PLL_Rx) = f(VCOx clock) / PLLRx   -> pllx_r_ck
19     f(PLL_Sx) = f(VCOx clock) / PLLSx   -> pllx_s_ck
20     f(PLL_Tx) = f(VCOx clock) / PLLTx   -> pllx_t_ck (only for PLL2)
25 compatible: "st,stm32h7rs-pll-clock"
27 include: st,stm32h7-pll-clock.yaml
30   div-s:
34         Valid range: 1 - 8
36   div-t:
40         Valid range: 1 - 8