Lines Matching +full:- +full:f

2 # SPDX-License-Identifier: Apache-2.0
14     f(PLLCLK) = f(PLLIN) x PLLMUL   --> SYSCLK (System Clock)
18               f(PLLIN) = f(input_clk) / PREDIV
21                 f(PLLIN) = f(input_clk) / 2
23                 f(PLLIN) = f(input_clk) / PREDIV
25   The PLL output frequency must be set in range 16-48MHz
27 compatible: "st,stm32f0-pll-clock"
30   - name: st,stm32f105-pll-clock.yaml
31     property-blocklist:
32       - mul
33       - otgfspre
41         Valid range: 2 - 16