Lines Matching +full:peripheral +full:- +full:in

2 # SPDX-License-Identifier: Apache-2.0
6   This node is in charge of system clock ('SYSCLK') source selection and controlling
7   clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
11   System clock source should be selected amongst the clock nodes available in "clocks"
13   Core clock frequency should also be defined, using "clock-frequency" property.
16   Last, peripheral bus clocks (typically PCLK1, PCLK2) should be configured using matching
21            ahb-prescaler = <2>;
22            clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23            apb1-prescaler = <1>;
24            apb2-prescaler = <1>;
29   To specify a gated clock, a peripheral should define a "clocks" property encoded
30   in the following way:
37   the bus controlling the peripheral and the second index specifies the bit used to
38   control the peripheral clock in that bus register.
39   The gated clock is required when accessing to the peripheral controller is needed
41   also used for peripheral operation.
53   In this example, I2C1 device is assigned HSI as domain clock source.
55   register while the gated clock is off. As it doesn't feed the peripheral's controller, it
56   allows peripheral operation, but can't be used for peripheral configuration.
57   It is peripheral driver's responsibility to query and use clock source information in
60   Since the peripheral subsystem rate is dictated by the clock used for peripheral
61   operation, same clock should be used in calls to `clock_control_get_rate()`
66   Note 2: Default peripheral clock configuration (ie the one provided in *.dsti files)
68           what is the reset value of the clock source for each peripheral.
81 compatible: "st,stm32-rcc"
83 include: [clock-controller.yaml, base.yaml]
89   "#clock-cells":
92   clock-frequency:
96       default frequency in Hz for clock output
98   ahb-prescaler:
102       - 1
103       - 2
104       - 4
105       - 8
106       - 16
107       - 64
108       - 128
109       - 256
110       - 512
116   apb1-prescaler:
120       - 1
121       - 2
122       - 4
123       - 8
124       - 16
126   apb2-prescaler:
130       - 1
131       - 2
132       - 4
133       - 8
134       - 16
136   undershoot-prevention:
140       (>80MHz) in two steps in order to prevent undershoot.
145 clock-cells:
146   - bus
147   - bits