Lines Matching +full:5 +full:- +full:10
2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
21 compatible: "nuvoton,npcx-pcc"
23 include: [clock-controller.yaml, base.yaml]
29 clock-frequency:
44 - 120000000
45 - 100000000
46 - 96000000
47 - 90000000
48 - 80000000
49 - 66000000
50 - 50000000
51 - 48000000
53 core-prescaler:
59 - CORE_CLK must be set to 4MHz <= CORE_CLK <= 100MHz.
65 5, CORE_CLK = OFMCLK / 5
70 10, CORE_CLK = OFMCLK / 10
72 - 1
73 - 2
74 - 3
75 - 4
76 - 5
77 - 6
78 - 7
79 - 8
80 - 9
81 - 10
83 apb1-prescaler:
89 - APB1_CLK must be set to 4MHz <= APB1_CLK <= 50MHz.
90 - APB1_CLK must be an integer division (including 1) of CORE_CLK.
96 5, APB1_CLK = OFMCLK / 5
101 10, APB1_CLK = OFMCLK / 10
103 - 1
104 - 2
105 - 3
106 - 4
107 - 5
108 - 6
109 - 7
110 - 8
111 - 9
112 - 10
114 apb2-prescaler:
120 - APB2_CLK must be set to 8MHz <= APB2_CLK <= 50MHz.
121 - APB2_CLK must be an integer division (including 1) of CORE_CLK.
127 5, APB2_CLK = OFMCLK / 5
132 10, APB2_CLK = OFMCLK / 10
134 - 1
135 - 2
136 - 3
137 - 4
138 - 5
139 - 6
140 - 7
141 - 8
142 - 9
143 - 10
145 apb3-prescaler:
151 - APB3_CLK must be set to 12.5MHz <= APB3_CLK <= 50MHz.
152 - APB3_CLK must be an integer division (including 1) of CORE_CLK.
158 5, APB3_CLK = OFMCLK / 5
163 10, APB3_CLK = OFMCLK / 10
165 - 1
166 - 2
167 - 3
168 - 4
169 - 5
170 - 6
171 - 7
172 - 8
173 - 9
174 - 10
176 apb4-prescaler:
181 - APB4_CLK must be set to 8MHz <= APB4_CLK <= 50MHz.
182 - APB4_CLK must be an integer division (including 1) of CORE_CLK.
188 5, APB4_CLK = OFMCLK / 5
193 10, APB4_CLK = OFMCLK / 10
195 - 1
196 - 2
197 - 3
198 - 4
199 - 5
200 - 6
201 - 7
202 - 8
203 - 9
204 - 10
206 ram-pd-depth:
209 - 8
210 - 12
211 - 15
213 Valid bit-depth of RAM block Power-Down control (RAM_PD) registers.
215 itself to 1 for better power consumption and this valid bit-depth
218 pwdwn-ctl-val:
222 Power-down (turn off clock) the modules during system initialization for
225 clock-cells:
226 - bus
227 - ctl
228 - bit