Lines Matching +full:pll +full:- +full:32 +full:k +full:- +full:src

2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-pcr"
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14   core-clock-div:
17     description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19   slow-clock-div:
25   pll-32k-src:
28     description: 32 KHz clock source for PLL
30   periph-32k-src:
33     description: 32 KHz clock source for peripherals
35   xtal-single-ended:
39   clk32kmon-period-min:
43       32KHz clock monitor minimum valid 32KHz period in 48MHz units
45   clk32kmon-period-max:
49       32KHz clock monitor maximum valid 32KHz period in 48MHz units
51   clk32kmon-duty-cycle-var-max:
56       the measured 32KHz high and low pulse widths.
58   clk32kmon-valid-min:
62       Minimum number of consecutive 32KHz pulses that pass all monitor tests
64   xtal-enable-delay-ms:
72   pll-lock-timeout-ms:
77       Timeout in milliseconds waiting for PLL to lock to new clock source.
79   clkmon-bypass:
81     description: Bypass clkmon check of crystal or XTAL2 single-ended clock.
83   internal-osc-disable:
86       If the internal silicon 32KHz oscillator is not chosen as the source
87       for PLL and Periheral devices then disable the internal 32KHz
90   "#clock-cells":
93 clock-cells:
94   - regidx
95   - bitpos
96   - domain