Lines Matching +full:stm32 +full:- +full:rcc
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv6-m.dtsi>
9 #include <zephyr/dt-bindings/clock/stm32u0_clock.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/adc/adc.h>
12 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/i2c/i2c.h>
17 #include <zephyr/dt-bindings/reset/stm32u0_reset.h>
22 zephyr,flash-controller = &flash;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 compatible = "arm,cortex-m0+";
34 #address-cells = <1>;
35 #size-cells = <1>;
40 compatible = "mmio-sram";
44 clk_hse: clk-hse {
45 #clock-cells = <0>;
46 compatible = "st,stm32-hse-clock";
50 clk_hsi: clk-hsi {
51 #clock-cells = <0>;
52 compatible = "fixed-clock";
53 clock-frequency = <DT_FREQ_M(16)>;
57 clk_hsi48: clk-hsi48 {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <DT_FREQ_M(48)>;
64 clk_msi: clk-msi {
65 #clock-cells = <0>;
66 compatible = "st,stm32-msi-clock";
67 msi-range = <4>; /* 4MHz (reset value) */
71 clk_lse: clk-lse {
72 #clock-cells = <0>;
73 compatible = "st,stm32-lse-clock";
74 clock-frequency = <32768>;
75 driving-capability = <2>;
79 clk_lsi: clk-lsi {
80 #clock-cells = <0>;
81 compatible = "fixed-clock";
82 clock-frequency = <DT_FREQ_K(32)>;
87 #clock-cells = <0>;
88 compatible = "st,stm32u0-pll-clock";
94 flash: flash-controller@40022000 {
95 compatible = "st,stm32-flash-controller", "st,stm32g0-flash-controller";
99 #address-cells = <1>;
100 #size-cells = <1>;
103 compatible = "st,stm32-nv-flash", "soc-nv-flash";
105 write-block-size = <8>;
106 erase-block-size = <2048>;
108 max-erase-time = <40>;
112 rcc: rcc@40021000 { label
113 compatible = "st,stm32f0-rcc";
114 clocks-controller;
115 #clock-cells = <2>;
118 rctl: reset-controller {
119 compatible = "st,stm32-rcc-rctl";
120 #reset-cells = <1>;
124 exti: interrupt-controller@40021800 {
125 compatible = "st,stm32g0-exti","st,stm32-exti";
126 interrupt-controller;
127 #interrupt-cells = <1>;
128 #address-cells = <1>;
130 num-lines = <16>;
132 interrupt-names = "line0-1", "line2-3", "line4-15";
133 line-ranges = <0 2>, <2 2>, <4 12>;
136 pinctrl: pin-controller@50000000 {
137 compatible = "st,stm32-pinctrl";
138 #address-cells = <1>;
139 #size-cells = <1>;
143 compatible = "st,stm32-gpio";
144 gpio-controller;
145 #gpio-cells = <2>;
147 clocks = <&rcc STM32_CLOCK(IOP, 0U)>;
151 compatible = "st,stm32-gpio";
152 gpio-controller;
153 #gpio-cells = <2>;
155 clocks = <&rcc STM32_CLOCK(IOP, 1U)>;
159 compatible = "st,stm32-gpio";
160 gpio-controller;
161 #gpio-cells = <2>;
163 clocks = <&rcc STM32_CLOCK(IOP, 2U)>;
167 compatible = "st,stm32-gpio";
168 gpio-controller;
169 #gpio-cells = <2>;
171 clocks = <&rcc STM32_CLOCK(IOP, 3U)>;
175 compatible = "st,stm32-gpio";
176 gpio-controller;
177 #gpio-cells = <2>;
179 clocks = <&rcc STM32_CLOCK(IOP, 4U)>;
183 compatible = "st,stm32-gpio";
184 gpio-controller;
185 #gpio-cells = <2>;
187 clocks = <&rcc STM32_CLOCK(IOP, 5U)>;
192 compatible = "st,stm32-usart", "st,stm32-uart";
194 clocks = <&rcc STM32_CLOCK(APB1_2, 14U)>;
201 compatible = "st,stm32-usart", "st,stm32-uart";
203 clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
210 compatible = "st,stm32-usart", "st,stm32-uart";
212 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
219 compatible = "st,stm32-lpuart", "st,stm32-uart";
221 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
228 compatible = "st,stm32-lpuart", "st,stm32-uart";
230 clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
237 compatible = "st,stm32-watchdog";
243 compatible = "st,stm32-window-watchdog";
245 clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
251 compatible = "st,stm32-adc";
253 clocks = <&rcc STM32_CLOCK(APB1_2, 20U)>;
256 #io-channel-cells = <1>;
261 sampling-times = <2 4 8 13 20 40 80 161>;
262 num-sampling-time-common-channels = <2>;
263 st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
264 st,adc-oversampler = "OVERSAMPLER_MINIMAL";
268 compatible = "st,stm32-dac";
270 clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
272 #io-channel-cells = <1>;
276 compatible = "st,stm32-i2c-v2";
277 clock-frequency = <I2C_BITRATE_STANDARD>;
278 #address-cells = <1>;
279 #size-cells = <0>;
281 clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
283 interrupt-names = "combined";
288 compatible = "st,stm32-i2c-v2";
289 clock-frequency = <I2C_BITRATE_STANDARD>;
290 #address-cells = <1>;
291 #size-cells = <0>;
293 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
295 interrupt-names = "combined";
300 compatible = "st,stm32-i2c-v2";
301 clock-frequency = <I2C_BITRATE_STANDARD>;
302 #address-cells = <1>;
303 #size-cells = <0>;
305 clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
307 interrupt-names = "combined";
312 compatible = "st,stm32-dma-v2";
313 #dma-cells = <3>;
316 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
317 dma-requests = <7>;
318 dma-offset = <0>;
323 compatible = "st,stm32-dmamux";
324 #dma-cells = <3>;
327 dma-channels = <7>;
328 dma-generators = <4>;
329 dma-requests= <76>;
334 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
335 #address-cells = <1>;
336 #size-cells = <0>;
338 clocks = <&rcc STM32_CLOCK(APB1_2, 12U)>;
344 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
345 #address-cells = <1>;
346 #size-cells = <0>;
348 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
354 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
355 #address-cells = <1>;
356 #size-cells = <0>;
358 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
364 compatible = "st,stm32-rng";
366 clocks = <&rcc STM32_CLOCK(AHB1, 18U)>;
372 compatible = "st,stm32-aes";
374 clocks = <&rcc STM32_CLOCK(AHB1, 16U)>;
377 interrupt-names = "aes";
382 compatible = "st,stm32-rtc";
385 clocks = <&rcc STM32_CLOCK(APB1, 10U)>;
387 alarms-count = <2>;
388 alrm-exti-line = <28>;
393 compatible = "st,stm32-timers";
395 clocks = <&rcc STM32_CLOCK(APB1_2, 11U)>;
398 interrupt-names = "brk_up_trg_com", "cc";
403 compatible = "st,stm32-pwm";
405 #pwm-cells = <3>;
409 compatible = "st,stm32-counter";
415 compatible = "st,stm32-timers";
417 clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
420 interrupt-names = "global";
425 compatible = "st,stm32-pwm";
427 #pwm-cells = <3>;
431 compatible = "st,stm32-counter";
437 compatible = "st,stm32-timers";
439 clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
442 interrupt-names = "global";
447 compatible = "st,stm32-pwm";
449 #pwm-cells = <3>;
453 compatible = "st,stm32-counter";
459 compatible = "st,stm32-timers";
461 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
464 interrupt-names = "combined";
470 compatible = "st,stm32-timers";
472 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
475 interrupt-names = "combined";
481 compatible = "st,stm32-timers";
483 clocks = <&rcc STM32_CLOCK(APB1_2, 16U)>;
486 interrupt-names = "combined";
491 compatible = "st,stm32-pwm";
493 #pwm-cells = <3>;
497 compatible = "st,stm32-counter";
503 compatible = "st,stm32-timers";
505 clocks = <&rcc STM32_CLOCK(APB1_2, 17U)>;
508 interrupt-names = "global";
513 compatible = "st,stm32-pwm";
515 #pwm-cells = <3>;
519 compatible = "st,stm32-counter";
525 compatible = "st,stm32-lptim";
526 clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
527 #address-cells = <1>;
528 #size-cells = <0>;
531 interrupt-names = "combined";
537 compatible = "st,stm32-lptim";
538 clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
539 #address-cells = <1>;
540 #size-cells = <0>;
543 interrupt-names = "combined";
550 arm,num-irq-priority-bits = <2>;