Lines Matching +full:dmamux +full:- +full:reg +full:- +full:offset
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv6-m.dtsi>
9 #include <zephyr/dt-bindings/clock/stm32u0_clock.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/adc/adc.h>
12 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/i2c/i2c.h>
17 #include <zephyr/dt-bindings/reset/stm32u0_reset.h>
22 zephyr,flash-controller = &flash;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 compatible = "arm,cortex-m0+";
33 reg = <0>;
34 #address-cells = <1>;
35 #size-cells = <1>;
40 compatible = "mmio-sram";
44 clk_hse: clk-hse {
45 #clock-cells = <0>;
46 compatible = "st,stm32-hse-clock";
50 clk_hsi: clk-hsi {
51 #clock-cells = <0>;
52 compatible = "fixed-clock";
53 clock-frequency = <DT_FREQ_M(16)>;
57 clk_hsi48: clk-hsi48 {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <DT_FREQ_M(48)>;
64 clk_msi: clk-msi {
65 #clock-cells = <0>;
66 compatible = "st,stm32-msi-clock";
67 msi-range = <4>; /* 4MHz (reset value) */
71 clk_lse: clk-lse {
72 #clock-cells = <0>;
73 compatible = "st,stm32-lse-clock";
74 clock-frequency = <32768>;
75 driving-capability = <2>;
79 clk_lsi: clk-lsi {
80 #clock-cells = <0>;
81 compatible = "fixed-clock";
82 clock-frequency = <DT_FREQ_K(32)>;
87 #clock-cells = <0>;
88 compatible = "st,stm32u0-pll-clock";
94 flash: flash-controller@40022000 {
95 compatible = "st,stm32-flash-controller", "st,stm32g0-flash-controller";
96 reg = <0x40022000 0x400>;
99 #address-cells = <1>;
100 #size-cells = <1>;
103 compatible = "st,stm32-nv-flash", "soc-nv-flash";
105 write-block-size = <8>;
106 erase-block-size = <2048>;
108 max-erase-time = <40>;
113 compatible = "st,stm32f0-rcc";
114 clocks-controller;
115 #clock-cells = <2>;
116 reg = <0x40021000 0x400>;
118 rctl: reset-controller {
119 compatible = "st,stm32-rcc-rctl";
120 #reset-cells = <1>;
124 exti: interrupt-controller@40021800 {
125 compatible = "st,stm32g0-exti","st,stm32-exti";
126 interrupt-controller;
127 #interrupt-cells = <1>;
128 #address-cells = <1>;
129 reg = <0x40021800 0x400>;
130 num-lines = <16>;
132 interrupt-names = "line0-1", "line2-3", "line4-15";
133 line-ranges = <0 2>, <2 2>, <4 12>;
136 pinctrl: pin-controller@50000000 {
137 compatible = "st,stm32-pinctrl";
138 #address-cells = <1>;
139 #size-cells = <1>;
140 reg = <0x50000000 0x2000>;
143 compatible = "st,stm32-gpio";
144 gpio-controller;
145 #gpio-cells = <2>;
146 reg = <0x50000000 0x400>;
151 compatible = "st,stm32-gpio";
152 gpio-controller;
153 #gpio-cells = <2>;
154 reg = <0x50000400 0x400>;
159 compatible = "st,stm32-gpio";
160 gpio-controller;
161 #gpio-cells = <2>;
162 reg = <0x50000800 0x400>;
167 compatible = "st,stm32-gpio";
168 gpio-controller;
169 #gpio-cells = <2>;
170 reg = <0x50000C00 0x400>;
175 compatible = "st,stm32-gpio";
176 gpio-controller;
177 #gpio-cells = <2>;
178 reg = <0x50001000 0x400>;
183 compatible = "st,stm32-gpio";
184 gpio-controller;
185 #gpio-cells = <2>;
186 reg = <0x50001400 0x400>;
192 compatible = "st,stm32-usart", "st,stm32-uart";
193 reg = <0x40013800 0x400>;
201 compatible = "st,stm32-usart", "st,stm32-uart";
202 reg = <0x40004400 0x400>;
210 compatible = "st,stm32-usart", "st,stm32-uart";
211 reg = <0x40004800 0x400>;
219 compatible = "st,stm32-usart", "st,stm32-uart";
220 reg = <0x40004c00 0x400>;
228 compatible = "st,stm32-lpuart", "st,stm32-uart";
229 reg = <0x40008000 0x400>;
237 compatible = "st,stm32-lpuart", "st,stm32-uart";
238 reg = <0x40008400 0x400>;
246 compatible = "st,stm32-watchdog";
247 reg = <0x40003000 0x400>;
252 compatible = "st,stm32-window-watchdog";
253 reg = <0x40002c00 0x400>;
260 compatible = "st,stm32-adc";
261 reg = <0x40012400 0x400>;
265 #io-channel-cells = <1>;
270 sampling-times = <2 4 8 13 20 40 80 161>;
271 num-sampling-time-common-channels = <2>;
272 st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
273 st,adc-oversampler = "OVERSAMPLER_MINIMAL";
277 compatible = "st,stm32-dac";
278 reg = <0x40007400 0x400>;
281 #io-channel-cells = <1>;
285 compatible = "st,stm32-i2c-v2";
286 clock-frequency = <I2C_BITRATE_STANDARD>;
287 #address-cells = <1>;
288 #size-cells = <0>;
289 reg = <0x40005400 0x400>;
292 interrupt-names = "combined";
297 compatible = "st,stm32-i2c-v2";
298 clock-frequency = <I2C_BITRATE_STANDARD>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 reg = <0x40005800 0x400>;
304 interrupt-names = "combined";
309 compatible = "st,stm32-i2c-v2";
310 clock-frequency = <I2C_BITRATE_STANDARD>;
311 #address-cells = <1>;
312 #size-cells = <0>;
313 reg = <0x40008800 0x400>;
316 interrupt-names = "combined";
321 compatible = "st,stm32-dma-v2";
322 #dma-cells = <3>;
323 reg = <0x40020000 0x400>;
326 dma-requests = <7>;
327 dma-offset = <0>;
331 dmamux1: dmamux@40020800 {
332 compatible = "st,stm32-dmamux";
333 #dma-cells = <3>;
334 reg = <0x40020800 0x400>;
336 dma-channels = <7>;
337 dma-generators = <4>;
338 dma-requests= <76>;
343 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
344 #address-cells = <1>;
345 #size-cells = <0>;
346 reg = <0x40013000 0x400>;
353 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
354 #address-cells = <1>;
355 #size-cells = <0>;
356 reg = <0x40003800 0x400>;
363 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
364 #address-cells = <1>;
365 #size-cells = <0>;
366 reg = <0x40003c00 0x400>;
373 compatible = "st,stm32-rng";
374 reg = <0x40025000 0x400>;
381 compatible = "st,stm32-aes";
382 reg = <0x40026000 0x400>;
386 interrupt-names = "aes";
391 compatible = "st,stm32-rtc";
392 reg = <0x40002800 0x400>;
396 alarms-count = <2>;
397 alrm-exti-line = <28>;
402 compatible = "st,stm32-timers";
403 reg = <0x40012C00 0x400>;
407 interrupt-names = "brk_up_trg_com", "cc";
412 compatible = "st,stm32-pwm";
414 #pwm-cells = <3>;
418 compatible = "st,stm32-counter";
424 compatible = "st,stm32-timers";
425 reg = <0x40000000 0x400>;
429 interrupt-names = "global";
434 compatible = "st,stm32-pwm";
436 #pwm-cells = <3>;
440 compatible = "st,stm32-counter";
446 compatible = "st,stm32-timers";
447 reg = <0x40000400 0x400>;
451 interrupt-names = "global";
456 compatible = "st,stm32-pwm";
458 #pwm-cells = <3>;
462 compatible = "st,stm32-counter";
468 compatible = "st,stm32-timers";
469 reg = <0x40001000 0x400>;
473 interrupt-names = "combined";
479 compatible = "st,stm32-timers";
480 reg = <0x40001400 0x400>;
484 interrupt-names = "combined";
490 compatible = "st,stm32-timers";
491 reg = <0x40014000 0x400>;
495 interrupt-names = "combined";
500 compatible = "st,stm32-pwm";
502 #pwm-cells = <3>;
506 compatible = "st,stm32-counter";
512 compatible = "st,stm32-timers";
513 reg = <0x40014400 0x400>;
517 interrupt-names = "global";
522 compatible = "st,stm32-pwm";
524 #pwm-cells = <3>;
528 compatible = "st,stm32-counter";
534 compatible = "st,stm32-lptim";
536 #address-cells = <1>;
537 #size-cells = <0>;
538 reg = <0x40007c00 0x400>;
540 interrupt-names = "combined";
546 compatible = "st,stm32-lptim";
548 #address-cells = <1>;
549 #size-cells = <0>;
550 reg = <0x40009400 0x400>;
552 interrupt-names = "combined";
556 compatible = "st,stm32-tsc";
557 reg = <0x40024000 0x400>;
561 interrupt-names = "global";
568 arm,num-irq-priority-bits = <2>;