Lines Matching +full:stm32 +full:- +full:rcc
5 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/clock/stm32_common_clocks.h>
13 #include <zephyr/dt-bindings/clock/stm32_clock.h>
14 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
16 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
17 #include <zephyr/dt-bindings/dma/stm32_dma.h>
18 #include <zephyr/dt-bindings/reset/stm32mp1_reset.h>
19 #include <zephyr/dt-bindings/display/panel.h>
23 #address-cells = <1>;
24 #size-cells = <0>;
28 compatible = "arm,cortex-m4";
34 compatible = "mmio-sram";
38 compatible = "mmio-sram";
43 compatible = "st,stm32mp157", "st,stm32mp1", "simple-bus";
45 rcc: rcc@50000000 { label
46 compatible = "st,stm32mp1-rcc";
48 #clock-cells = <2>;
50 rctl: reset-controller {
51 compatible = "st,stm32-rcc-rctl";
52 #reset-cells = <1>;
53 set-bit-to-deassert;
57 exti: interrupt-controller@5000d000 {
58 compatible = "st,stm32g0-exti", "st,stm32-exti";
59 interrupt-controller;
60 #interrupt-cells = <1>;
61 #address-cells = <1>;
63 num-lines = <16>;
68 interrupt-names = "line0", "line1", "line2", "line3",
72 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
78 pinctrl: pin-controller@50002000 {
79 compatible = "st,stm32-pinctrl";
81 #address-cells = <1>;
82 #size-cells = <1>;
85 compatible = "st,stm32-gpio";
87 gpio-controller;
88 #gpio-cells = <2>;
89 clocks = <&rcc STM32_CLOCK(AHB4, 0U)>;
93 compatible = "st,stm32-gpio";
95 gpio-controller;
96 #gpio-cells = <2>;
97 clocks = <&rcc STM32_CLOCK(AHB4, 1U)>;
101 compatible = "st,stm32-gpio";
103 gpio-controller;
104 #gpio-cells = <2>;
105 clocks = <&rcc STM32_CLOCK(AHB4, 2U)>;
109 compatible = "st,stm32-gpio";
111 gpio-controller;
112 #gpio-cells = <2>;
113 clocks = <&rcc STM32_CLOCK(AHB4, 3U)>;
117 compatible = "st,stm32-gpio";
119 gpio-controller;
120 #gpio-cells = <2>;
121 clocks = <&rcc STM32_CLOCK(AHB4, 4U)>;
125 compatible = "st,stm32-gpio";
127 gpio-controller;
128 #gpio-cells = <2>;
129 clocks = <&rcc STM32_CLOCK(AHB4, 5U)>;
133 compatible = "st,stm32-gpio";
135 gpio-controller;
136 #gpio-cells = <2>;
137 clocks = <&rcc STM32_CLOCK(AHB4, 6U)>;
141 compatible = "st,stm32-gpio";
143 gpio-controller;
144 #gpio-cells = <2>;
145 clocks = <&rcc STM32_CLOCK(AHB4, 7U)>;
149 compatible = "st,stm32-gpio";
151 gpio-controller;
152 #gpio-cells = <2>;
153 clocks = <&rcc STM32_CLOCK(AHB4, 8U)>;
157 compatible = "st,stm32-gpio";
159 gpio-controller;
160 #gpio-cells = <2>;
161 clocks = <&rcc STM32_CLOCK(AHB4, 9U)>;
165 compatible = "st,stm32-gpio";
167 gpio-controller;
168 #gpio-cells = <2>;
169 clocks = <&rcc STM32_CLOCK(AHB4, 10U)>;
174 compatible = "st,stm32-window-watchdog";
176 clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
182 compatible = "st,stm32-dma-v1";
183 #dma-cells = <4>;
185 clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
187 dma-offset = <0>;
188 dma-requests = <8>;
193 compatible = "st,stm32-dma-v1";
194 #dma-cells = <4>;
196 clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
198 dma-offset = <8>;
199 dma-requests = <8>;
204 compatible = "st,stm32-dmamux";
205 #dma-cells = <3>;
207 clocks = <&rcc STM32_CLOCK(AHB2, 2U)>;
209 dma-channels = <16>;
210 dma-generators = <8>;
211 dma-requests= <108>;
216 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
218 #address-cells = <1>;
219 #size-cells = <0>;
220 clocks = <&rcc STM32_CLOCK(APB2, 8U)>;
226 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
228 #address-cells = <1>;
229 #size-cells = <0>;
230 clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
236 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
238 #address-cells = <1>;
239 #size-cells = <0>;
240 clocks = <&rcc STM32_CLOCK(APB1, 12U)>;
246 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
248 #address-cells = <1>;
249 #size-cells = <0>;
250 clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
256 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
258 #address-cells = <1>;
259 #size-cells = <0>;
260 clocks = <&rcc STM32_CLOCK(APB2, 10U)>;
266 compatible = "st,stm32-usart", "st,stm32-uart";
268 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
275 compatible = "st,stm32-usart", "st,stm32-uart";
277 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
284 compatible = "st,stm32-uart";
286 clocks = <&rcc STM32_CLOCK(APB1, 16U)>;
293 compatible = "st,stm32-uart";
295 clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
302 compatible = "st,stm32-usart", "st,stm32-uart";
304 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
311 compatible = "st,stm32-uart";
313 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
320 compatible = "st,stm32-uart";
322 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
329 compatible = "st,stm32-i2c-v2";
330 clock-frequency = <I2C_BITRATE_STANDARD>;
332 #address-cells = <1>;
333 #size-cells = <0>;
334 clocks = <&rcc STM32_CLOCK(APB1, 24U)>;
335 interrupt-names = "event", "error";
341 compatible = "st,stm32-timers";
343 clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
346 interrupt-names = "global";
351 compatible = "st,stm32-pwm";
353 #pwm-cells = <3>;
357 compatible = "st,stm32-counter";
363 compatible = "st,stm32-timers";
365 clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
368 interrupt-names = "global";
373 compatible = "st,stm32-pwm";
375 #pwm-cells = <3>;
379 compatible = "st,stm32-counter";
385 compatible = "st,stm32-ipcc-mailbox";
387 clocks = <&rcc STM32_CLOCK(AHB3, 12U)>;
389 interrupt-names = "rxo", "txf";
393 ltdc: display-controller@5a001000 {
394 compatible = "st,stm32-ltdc";
397 interrupt-names = "ltdc", "ltdc_er";
398 clocks = <&rcc STM32_CLOCK(APB4, 0U)>;
405 compatible = "st,stm32-smbus";
406 #address-cells = <1>;
407 #size-cells = <0>;
414 arm,num-irq-priority-bits = <4>;