Lines Matching +full:stm32 +full:- +full:rcc
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/flash_controller/ospi.h>
11 /delete-node/ &quadspi;
26 clk_hsi48: clk-hsi48 {
27 #clock-cells = <0>;
28 compatible = "fixed-clock";
29 clock-frequency = <DT_FREQ_M(48)>;
35 compatible = "st,stm32l4p5", "st,stm32l4", "simple-bus";
38 flash-controller@40022000 {
40 erase-block-size = <4096>;
44 rcc: rcc@40021000 { label
45 undershoot-prevention;
49 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
50 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
53 pinctrl: pin-controller@48000000 {
57 compatible = "st,stm32-gpio";
58 gpio-controller;
59 #gpio-cells = <2>;
61 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
65 compatible = "st,stm32-gpio";
66 gpio-controller;
67 #gpio-cells = <2>;
69 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
73 compatible = "st,stm32-gpio";
74 gpio-controller;
75 #gpio-cells = <2>;
77 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
81 compatible = "st,stm32-gpio";
82 gpio-controller;
83 #gpio-cells = <2>;
85 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
89 compatible = "st,stm32-gpio";
90 gpio-controller;
91 #gpio-cells = <2>;
93 clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
98 compatible = "st,stm32-usart", "st,stm32-uart";
100 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
107 compatible = "st,stm32-uart";
109 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
116 compatible = "st,stm32-uart";
118 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
125 compatible = "st,stm32-i2c-v2";
126 clock-frequency = <I2C_BITRATE_STANDARD>;
127 #address-cells = <1>;
128 #size-cells = <0>;
130 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
132 interrupt-names = "event", "error";
137 compatible = "st,stm32-i2c-v2";
138 clock-frequency = <I2C_BITRATE_STANDARD>;
139 #address-cells = <1>;
140 #size-cells = <0>;
142 clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>;
144 interrupt-names = "event", "error";
149 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
150 #address-cells = <1>;
151 #size-cells = <0>;
153 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
159 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
160 #address-cells = <1>;
161 #size-cells = <0>;
163 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
169 compatible = "st,stm32-timers";
171 clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
174 interrupt-names = "global";
179 compatible = "st,stm32-pwm";
181 #pwm-cells = <3>;
185 compatible = "st,stm32-counter";
191 compatible = "st,stm32-timers";
193 clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
196 interrupt-names = "global";
201 compatible = "st,stm32-pwm";
203 #pwm-cells = <3>;
207 compatible = "st,stm32-counter";
213 compatible = "st,stm32-timers";
215 clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
218 interrupt-names = "global";
223 compatible = "st,stm32-pwm";
225 #pwm-cells = <3>;
229 compatible = "st,stm32-counter";
235 compatible = "st,stm32-timers";
237 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
240 interrupt-names = "global";
245 compatible = "st,stm32-pwm";
247 #pwm-cells = <3>;
251 compatible = "st,stm32-counter";
257 compatible = "st,stm32-timers";
259 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
262 interrupt-names = "brk", "up", "trgcom", "cc";
267 compatible = "st,stm32-pwm";
269 #pwm-cells = <3>;
274 compatible = "st,stm32-timers";
276 clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
279 interrupt-names = "global";
284 compatible = "st,stm32-pwm";
286 #pwm-cells = <3>;
290 compatible = "st,stm32-counter";
296 compatible = "st,stm32-bxcan";
299 interrupt-names = "TX", "RX0", "RX1", "SCE";
300 clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN
305 compatible = "st,stm32-otgfs";
308 interrupt-names = "otgfs";
309 num-bidir-endpoints = <6>;
310 ram-size = <1280>;
311 maximum-speed = "full-speed";
312 clocks = <&rcc STM32_CLOCK(AHB2, 12U)>,
313 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
319 dma-offset = <0>;
323 dma-offset = <7>;
327 compatible = "st,stm32-dmamux";
328 #dma-cells = <3>;
331 clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
332 dma-channels = <14>;
333 dma-generators = <4>;
334 dma-requests= <89>;
339 compatible = "st,stm32-sdmmc";
341 clocks = <&rcc STM32_CLOCK(AHB2, 22U)>,
342 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
349 compatible = "st,stm32-sdmmc";
351 clocks = <&rcc STM32_CLOCK(AHB2, 23U)>,
352 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
359 compatible = "st,stm32-dac";
361 clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
363 #io-channel-cells = <1>;
367 compatible = "st,stm32-ospi";
370 clock-names = "ospix", "ospi-ker", "ospi-mgr";
371 clocks = <&rcc STM32_CLOCK(AHB3, 8U)>,
372 <&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>,
373 <&rcc STM32_CLOCK(AHB2, 20U)>;
375 #address-cells = <1>;
376 #size-cells = <0>;
381 compatible = "st,stm32-ospi";
384 clock-names = "ospix", "ospi-ker", "ospi-mgr";
385 clocks = <&rcc STM32_CLOCK(AHB3, 9U)>,
386 <&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>,
387 <&rcc STM32_CLOCK(AHB2, 20U)>;
389 #address-cells = <1>;
390 #size-cells = <0>;
396 compatible = "usb-nop-xceiv";
397 #phy-cells = <0>;
401 compatible = "st,stm32-smbus";
402 #address-cells = <1>;
403 #size-cells = <0>;
409 compatible = "st,stm32-smbus";
410 #address-cells = <1>;
411 #size-cells = <0>;