Lines Matching +full:stm32 +full:- +full:rcc
6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32l1_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/adc/adc.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/stm32f4_adc.h>
18 #include <zephyr/dt-bindings/reset/stm32l1_reset.h>
23 zephyr,flash-controller = &flash;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 compatible = "arm,cortex-m3";
38 compatible = "mmio-sram";
42 clk_hse: clk-hse {
43 #clock-cells = <0>;
44 compatible = "st,stm32-hse-clock";
48 clk_hsi: clk-hsi {
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <DT_FREQ_M(16)>;
55 clk_msi: clk-msi {
56 #clock-cells = <0>;
57 compatible = "st,stm32l0-msi-clock";
58 msi-range = <5>; /* 2.1MHz (reset value) */
62 clk_lse: clk-lse {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <32768>;
69 clk_lsi: clk-lsi {
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <DT_FREQ_K(37)>;
77 #clock-cells = <0>;
78 compatible = "st,stm32l0-pll-clock";
85 flash: flash-controller@40023c00 {
86 compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
89 clocks = <&rcc STM32_CLOCK(AHB1, 15U)>;
91 #address-cells = <1>;
92 #size-cells = <1>;
95 compatible = "st,stm32f4-nv-flash", "st,stm32-nv-flash",
96 "soc-nv-flash";
98 write-block-size = <4>;
99 /* maximum erase time(ms) for a 128B half-page
101 max-erase-time = <4>;
105 rcc: rcc@40023800 { label
106 compatible = "st,stm32-rcc";
107 #clock-cells = <2>;
110 rctl: reset-controller {
111 compatible = "st,stm32-rcc-rctl";
112 #reset-cells = <1>;
117 compatible = "st,stm32-rtc";
120 clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
122 alarms-count = <2>;
123 alrm-exti-line = <17>;
128 compatible = "st,stm32-usart", "st,stm32-uart";
130 clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
137 compatible = "st,stm32-usart", "st,stm32-uart";
139 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
146 compatible = "st,stm32-uart";
148 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
155 compatible = "st,stm32-uart";
157 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
164 compatible = "st,stm32-i2c-v1";
165 clock-frequency = <I2C_BITRATE_STANDARD>;
166 #address-cells = <1>;
167 #size-cells = <0>;
169 clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
171 interrupt-names = "event", "error";
176 compatible = "st,stm32-i2c-v1";
177 clock-frequency = <I2C_BITRATE_STANDARD>;
178 #address-cells = <1>;
179 #size-cells = <0>;
181 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
183 interrupt-names = "event", "error";
188 compatible = "st,stm32-spi";
189 #address-cells = <1>;
190 #size-cells = <0>;
192 clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
198 compatible = "st,stm32-spi";
199 #address-cells = <1>;
200 #size-cells = <0>;
202 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
208 compatible = "st,stm32-usart", "st,stm32-uart";
210 clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
217 compatible = "st,stm32f4-adc", "st,stm32-adc";
219 clocks = <&rcc STM32_CLOCK(APB2, 9U)>,
220 <&rcc STM32_SRC_HSI NO_SEL>;
223 #io-channel-cells = <1>;
228 sampling-times = <4 9 16 24 48 96 192 384>;
229 st,adc-clock-source = "ASYNC";
230 st,adc-sequencer = "FULLY_CONFIGURABLE";
231 st,adc-oversampler = "OVERSAMPLER_NONE";
235 compatible = "st,stm32-dac";
237 clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
239 #io-channel-cells = <1>;
242 exti: interrupt-controller@40010400 {
243 compatible = "st,stm32-exti";
244 interrupt-controller;
245 #interrupt-cells = <1>;
246 #address-cells = <1>;
248 num-lines = <16>;
251 interrupt-names = "line0", "line1", "line2", "line3",
252 "line4", "line5-9", "line10-15";
253 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
258 compatible = "st,stm32-timers";
260 clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
263 interrupt-names = "global";
268 compatible = "st,stm32-pwm";
270 #pwm-cells = <3>;
274 compatible = "st,stm32-counter";
280 compatible = "st,stm32-timers";
282 clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
285 interrupt-names = "global";
290 compatible = "st,stm32-pwm";
292 #pwm-cells = <3>;
296 compatible = "st,stm32-counter";
302 compatible = "st,stm32-timers";
304 clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
307 interrupt-names = "global";
312 compatible = "st,stm32-pwm";
314 #pwm-cells = <3>;
318 compatible = "st,stm32-counter";
324 compatible = "st,stm32-timers";
326 clocks = <&rcc STM32_CLOCK(APB2, 2U)>;
329 interrupt-names = "global";
334 compatible = "st,stm32-pwm";
336 #pwm-cells = <3>;
340 compatible = "st,stm32-counter";
346 compatible = "st,stm32-timers";
348 clocks = <&rcc STM32_CLOCK(APB2, 3U)>;
351 interrupt-names = "global";
356 compatible = "st,stm32-pwm";
358 #pwm-cells = <3>;
362 compatible = "st,stm32-counter";
368 compatible = "st,stm32-timers";
370 clocks = <&rcc STM32_CLOCK(APB2, 4U)>;
373 interrupt-names = "global";
378 compatible = "st,stm32-pwm";
380 #pwm-cells = <3>;
384 compatible = "st,stm32-counter";
389 pinctrl: pin-controller@40020000 {
390 compatible = "st,stm32-pinctrl";
391 #address-cells = <1>;
392 #size-cells = <1>;
396 compatible = "st,stm32-gpio";
397 gpio-controller;
398 #gpio-cells = <2>;
400 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
404 compatible = "st,stm32-gpio";
405 gpio-controller;
406 #gpio-cells = <2>;
408 clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
412 compatible = "st,stm32-gpio";
413 gpio-controller;
414 #gpio-cells = <2>;
416 clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
420 compatible = "st,stm32-gpio";
421 gpio-controller;
422 #gpio-cells = <2>;
424 clocks = <&rcc STM32_CLOCK(AHB1, 3U)>;
428 compatible = "st,stm32-gpio";
429 gpio-controller;
430 #gpio-cells = <2>;
432 clocks = <&rcc STM32_CLOCK(AHB1, 4U)>;
436 compatible = "st,stm32-gpio";
437 gpio-controller;
438 #gpio-cells = <2>;
440 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
445 compatible = "st,stm32-watchdog";
451 compatible = "st,stm32-window-watchdog";
453 clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
459 compatible = "st,stm32-eeprom";
464 compatible = "st,stm32-dma-v2bis";
465 #dma-cells = <2>;
467 clocks = <&rcc STM32_CLOCK(AHB1, 24U)>;
474 compatible = "st,stm32-temp-cal";
475 ts-cal1-addr = <0x1FF800FA>;
476 ts-cal2-addr = <0x1FF800FE>;
477 ts-cal1-temp = <30>;
478 ts-cal2-temp = <110>;
479 ts-cal-vrefanalog = <3000>;
480 io-channels = <&adc1 16>;
485 compatible = "st,stm32-vref";
486 vrefint-cal-addr = <0x1FF800F8>;
487 vrefint-cal-mv = <3000>;
488 io-channels = <&adc1 17>;
493 compatible = "st,stm32-smbus";
494 #address-cells = <1>;
495 #size-cells = <0>;
501 compatible = "st,stm32-smbus";
502 #address-cells = <1>;
503 #size-cells = <0>;
510 arm,num-irq-priority-bits = <4>;