Lines Matching +full:stm32 +full:- +full:rcc
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/clock/stm32h7rs_clock.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
13 #include <zephyr/dt-bindings/reset/stm32h7rs_reset.h>
14 #include <zephyr/dt-bindings/adc/stm32h7_adc.h>
15 #include <zephyr/dt-bindings/adc/adc.h>
16 #include <zephyr/dt-bindings/memory-attr/memory-attr.h>
17 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
27 zephyr,flash-controller = &flash;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 compatible = "arm,cortex-m7";
38 #address-cells = <1>;
39 #size-cells = <1>;
42 compatible = "arm,armv7m-mpu";
50 compatible = "mmio-sram";
57 compatible = "zephyr,memory-region", "mmio-sram";
58 zephyr,memory-region = "SRAM1";
63 compatible = "zephyr,memory-region", "mmio-sram";
65 zephyr,memory-region = "SRAM2";
69 compatible = "zephyr,memory-region", "arm,dtcm";
71 zephyr,memory-region = "DTCM";
75 compatible = "zephyr,memory-region", "arm,itcm";
77 zephyr,memory-region = "ITCM";
81 compatible = "zephyr,memory-region";
83 zephyr,memory-region = "EXTMEM";
84 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>;
88 #address-cells = <1>;
89 #size-cells = <0>;
91 clk_hse: clk-hse {
92 #clock-cells = <0>;
93 compatible = "st,stm32-hse-clock";
97 clk_hsi: clk-hsi {
98 #clock-cells = <0>;
99 compatible = "st,stm32h7-hsi-clock";
100 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
101 clock-frequency = <DT_FREQ_M(64)>;
105 clk_hsi48: clk-hsi48 {
106 #clock-cells = <0>;
107 compatible = "fixed-clock";
108 clock-frequency = <DT_FREQ_M(48)>;
112 clk_csi: clk-csi {
113 #clock-cells = <0>;
114 compatible = "fixed-clock";
115 clock-frequency = <DT_FREQ_M(4)>;
119 clk_lse: clk-lse {
120 #clock-cells = <0>;
121 compatible = "st,stm32-lse-clock";
122 clock-frequency = <32768>;
123 driving-capability = <0>;
127 clk_lsi: clk-lsi {
128 #clock-cells = <0>;
129 compatible = "fixed-clock";
130 clock-frequency = <DT_FREQ_K(32)>;
135 #clock-cells = <0>;
136 compatible = "st,stm32h7rs-pll-clock";
142 #clock-cells = <0>;
143 compatible = "st,stm32h7rs-pll-clock";
149 #clock-cells = <0>;
150 compatible = "st,stm32h7rs-pll-clock";
156 #clock-cells = <0>;
157 compatible = "st,stm32-clock-mux";
164 compatible = "st,stm32-clock-mco";
169 compatible = "st,stm32-clock-mco";
175 flash: flash-controller@52002000 {
176 compatible = "st,stm32-flash-controller", "st,stm32h7-flash-controller";
179 clocks = <&rcc STM32_CLOCK(AHB3, 8U)>;
181 #address-cells = <1>;
182 #size-cells = <1>;
185 compatible = "st,stm32-nv-flash", "soc-nv-flash";
186 write-block-size = <32>;
187 erase-block-size = <DT_SIZE_K(8)>;
189 max-erase-time = <3>;
193 rcc: rcc@58024400 { label
194 compatible = "st,stm32h7rs-rcc";
195 #clock-cells = <2>;
198 rctl: reset-controller {
199 compatible = "st,stm32-rcc-rctl";
200 #reset-cells = <1>;
204 exti: interrupt-controller@58000000 {
205 compatible = "st,stm32h7rs-exti", "st,stm32-exti";
206 interrupt-controller;
207 #interrupt-cells = <1>;
208 #address-cells = <1>;
211 num-lines = <16>;
216 interrupt-names = "line0", "line1", "line2", "line3",
220 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
226 pinctrl: pin-controller@58020000 {
227 compatible = "st,stm32-pinctrl";
228 #address-cells = <1>;
229 #size-cells = <1>;
233 compatible = "st,stm32-gpio";
234 gpio-controller;
235 #gpio-cells = <2>;
237 clocks = <&rcc STM32_CLOCK(AHB4, 0U)>;
241 compatible = "st,stm32-gpio";
242 gpio-controller;
243 #gpio-cells = <2>;
245 clocks = <&rcc STM32_CLOCK(AHB4, 1U)>;
249 compatible = "st,stm32-gpio";
250 gpio-controller;
251 #gpio-cells = <2>;
253 clocks = <&rcc STM32_CLOCK(AHB4, 2U)>;
257 compatible = "st,stm32-gpio";
258 gpio-controller;
259 #gpio-cells = <2>;
261 clocks = <&rcc STM32_CLOCK(AHB4, 3U)>;
265 compatible = "st,stm32-gpio";
266 gpio-controller;
267 #gpio-cells = <2>;
269 clocks = <&rcc STM32_CLOCK(AHB4, 4U)>;
273 compatible = "st,stm32-gpio";
274 gpio-controller;
275 #gpio-cells = <2>;
277 clocks = <&rcc STM32_CLOCK(AHB4, 5U)>;
281 compatible = "st,stm32-gpio";
282 gpio-controller;
283 #gpio-cells = <2>;
285 clocks = <&rcc STM32_CLOCK(AHB4, 6U)>;
289 compatible = "st,stm32-gpio";
290 gpio-controller;
291 #gpio-cells = <2>;
293 clocks = <&rcc STM32_CLOCK(AHB4, 7U)>;
297 compatible = "st,stm32-gpio";
298 gpio-controller;
299 #gpio-cells = <2>;
301 clocks = <&rcc STM32_CLOCK(AHB4, 12U)>;
305 compatible = "st,stm32-gpio";
306 gpio-controller;
307 #gpio-cells = <2>;
309 clocks = <&rcc STM32_CLOCK(AHB4, 13U)>;
313 compatible = "st,stm32-gpio";
314 gpio-controller;
315 #gpio-cells = <2>;
317 clocks = <&rcc STM32_CLOCK(AHB4, 14U)>;
321 compatible = "st,stm32-gpio";
322 gpio-controller;
323 #gpio-cells = <2>;
325 clocks = <&rcc STM32_CLOCK(AHB4, 15U)>;
330 compatible = "st,stm32-usart", "st,stm32-uart";
332 clocks = <&rcc STM32_CLOCK(APB2, 4U)>;
338 compatible = "st,stm32-usart", "st,stm32-uart";
340 clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
346 compatible = "st,stm32-usart", "st,stm32-uart";
348 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
354 compatible ="st,stm32-uart";
356 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
362 compatible = "st,stm32-uart";
364 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
370 compatible = "st,stm32-uart";
372 clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
378 compatible = "st,stm32-uart";
380 clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
387 compatible = "st,stm32-lpuart", "st,stm32-uart";
389 clocks = <&rcc STM32_CLOCK(APB4, 3U)>;
396 compatible = "st,stm32-i2c-v2";
397 clock-frequency = <I2C_BITRATE_STANDARD>;
398 #address-cells = <1>;
399 #size-cells = <0>;
401 clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
403 interrupt-names = "event", "error";
408 compatible = "st,stm32-i2c-v2";
409 clock-frequency = <I2C_BITRATE_STANDARD>;
410 #address-cells = <1>;
411 #size-cells = <0>;
413 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
415 interrupt-names = "event", "error";
420 compatible = "st,stm32-i2c-v2";
421 clock-frequency = <I2C_BITRATE_STANDARD>;
422 #address-cells = <1>;
423 #size-cells = <0>;
425 clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
427 interrupt-names = "event", "error";
432 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
433 #address-cells = <1>;
434 #size-cells = <0>;
436 clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
437 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>;
443 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
444 #address-cells = <1>;
445 #size-cells = <0>;
447 clocks = <&rcc STM32_CLOCK(APB1, 14U)>,
448 <&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>;
454 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
455 #address-cells = <1>;
456 #size-cells = <0>;
458 clocks = <&rcc STM32_CLOCK(APB1, 15U)>,
459 <&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>;
465 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
466 #address-cells = <1>;
467 #size-cells = <0>;
469 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
475 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
476 #address-cells = <1>;
477 #size-cells = <0>;
479 clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
485 compatible = "st,stm32h7-i2s", "st,stm32-i2s";
486 #address-cells = <1>;
487 #size-cells = <0>;
489 clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
490 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>;
496 compatible = "st,stm32-watchdog";
503 compatible = "st,stm32-window-watchdog";
505 clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
511 compatible = "st,stm32-timers";
513 clocks = <&rcc STM32_CLOCK(APB2, 0U)>;
516 interrupt-names = "brk", "up", "trgcom", "cc";
521 compatible = "st,stm32-pwm";
523 #pwm-cells = <3>;
528 compatible = "st,stm32-timers";
530 clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
533 interrupt-names = "global";
538 compatible = "st,stm32-pwm";
540 #pwm-cells = <3>;
544 compatible = "st,stm32-counter";
550 compatible = "st,stm32-timers";
552 clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
555 interrupt-names = "global";
560 compatible = "st,stm32-pwm";
562 #pwm-cells = <3>;
566 compatible = "st,stm32-counter";
572 compatible = "st,stm32-timers";
574 clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
577 interrupt-names = "global";
582 compatible = "st,stm32-pwm";
584 #pwm-cells = <3>;
588 compatible = "st,stm32-counter";
594 compatible = "st,stm32-timers";
596 clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
599 interrupt-names = "global";
604 compatible = "st,stm32-pwm";
606 #pwm-cells = <3>;
610 compatible = "st,stm32-counter";
616 compatible = "st,stm32-timers";
618 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
621 interrupt-names = "global";
626 compatible = "st,stm32-counter";
632 compatible = "st,stm32-timers";
634 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
637 interrupt-names = "global";
642 compatible = "st,stm32-counter";
648 compatible = "st,stm32-timers";
650 clocks = <&rcc STM32_CLOCK(APB2, 19U)>;
653 interrupt-names = "global";
658 compatible = "st,stm32-counter";
664 compatible = "st,stm32-timers";
666 clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
669 interrupt-names = "global";
674 compatible = "st,stm32-pwm";
676 #pwm-cells = <3>;
680 compatible = "st,stm32-counter";
686 compatible = "st,stm32-timers";
688 clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
691 interrupt-names = "global";
696 compatible = "st,stm32-pwm";
698 #pwm-cells = <3>;
702 compatible = "st,stm32-counter";
708 compatible = "st,stm32-timers";
710 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
713 interrupt-names = "global";
718 compatible = "st,stm32-pwm";
720 #pwm-cells = <3>;
724 compatible = "st,stm32-counter";
730 compatible = "st,stm32-lptim";
731 clocks = <&rcc STM32_CLOCK(APB1, 9U)>;
732 #address-cells = <1>;
733 #size-cells = <0>;
736 interrupt-names = "wakeup";
741 compatible = "st,stm32-adc";
743 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
746 #io-channel-cells = <1>;
751 sampling-times = <3 7 13 25 48 93 248 641>;
752 st,adc-sequencer = "FULLY_CONFIGURABLE";
753 st,adc-oversampler = "OVERSAMPLER_MINIMAL";
757 compatible = "st,stm32-adc";
759 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
762 #io-channel-cells = <1>;
767 sampling-times = <3 7 13 25 48 93 248 641>;
768 st,adc-sequencer = "FULLY_CONFIGURABLE";
769 st,adc-oversampler = "OVERSAMPLER_MINIMAL";
773 compatible = "st,stm32-rng";
775 clocks = <&rcc STM32_CLOCK(AHB3, 0U)>;
782 compatible = "st,stm32-temp-cal";
783 ts-cal1-addr = <0x08FFF814>;
784 ts-cal2-addr = <0x08FFF818>;
785 ts-cal1-temp = <30>;
786 ts-cal2-temp = <130>;
787 ts-cal-vrefanalog = <3300>;
788 ts-cal-resolution = <12>;
789 io-channels = <&adc1 16>;
794 compatible = "st,stm32-vbat";
797 io-channels = <&adc2 16>;
801 compatible = "st,stm32-vref";
802 vrefint-cal-addr = <0x08fff810>;
803 vrefint-cal-mv = <3300>;
805 io-channels = <&adc1 17>;
810 arm,num-irq-priority-bits = <4>;