Lines Matching +full:stm32 +full:- +full:rcc
7 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/clock/stm32h7_clock.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/stm32h7_adc.h>
18 #include <zephyr/dt-bindings/reset/stm32h7_reset.h>
19 #include <zephyr/dt-bindings/adc/adc.h>
20 #include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h>
21 #include <zephyr/dt-bindings/memory-attr/memory-attr.h>
22 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
28 zephyr,flash-controller = &flash;
32 #address-cells = <1>;
33 #size-cells = <0>;
37 compatible = "arm,cortex-m7";
39 #address-cells = <1>;
40 #size-cells = <1>;
43 compatible = "arm,armv7m-mpu";
50 compatible = "zephyr,memory-region";
52 zephyr,memory-region = "EXTMEM";
53 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>;
57 #address-cells = <1>;
58 #size-cells = <0>;
60 clk_hse: clk-hse {
61 #clock-cells = <0>;
62 compatible = "st,stm32-hse-clock";
66 clk_hsi: clk-hsi {
67 #clock-cells = <0>;
68 compatible = "st,stm32h7-hsi-clock";
69 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
70 clock-frequency = <DT_FREQ_M(64)>;
74 clk_hsi48: clk-hsi48 {
75 #clock-cells = <0>;
76 compatible = "fixed-clock";
77 clock-frequency = <DT_FREQ_M(48)>;
81 clk_csi: clk-csi {
82 #clock-cells = <0>;
83 compatible = "fixed-clock";
84 clock-frequency = <DT_FREQ_M(4)>;
88 clk_lse: clk-lse {
89 #clock-cells = <0>;
90 compatible = "st,stm32-lse-clock";
91 clock-frequency = <32768>;
92 driving-capability = <0>;
96 clk_lsi: clk-lsi {
97 #clock-cells = <0>;
98 compatible = "fixed-clock";
99 clock-frequency = <DT_FREQ_K(32)>;
104 #clock-cells = <0>;
105 compatible = "st,stm32h7-pll-clock";
111 #clock-cells = <0>;
112 compatible = "st,stm32h7-pll-clock";
118 #clock-cells = <0>;
119 compatible = "st,stm32h7-pll-clock";
125 #clock-cells = <0>;
126 compatible = "st,stm32-clock-mux";
133 compatible = "st,stm32-clock-mco";
138 compatible = "st,stm32-clock-mco";
144 flash: flash-controller@52002000 {
145 compatible = "st,stm32-flash-controller", "st,stm32h7-flash-controller";
149 #address-cells = <1>;
150 #size-cells = <1>;
153 rcc: rcc@58024400 { label
154 compatible = "st,stm32h7-rcc";
155 #clock-cells = <2>;
158 rctl: reset-controller {
159 compatible = "st,stm32-rcc-rctl";
160 #reset-cells = <1>;
164 exti: interrupt-controller@58000000 {
165 compatible = "st,stm32-exti";
166 interrupt-controller;
167 #interrupt-cells = <1>;
168 #address-cells = <1>;
170 num-lines = <16>;
173 interrupt-names = "line0", "line1", "line2", "line3",
174 "line4", "line5-9", "line10-15";
175 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
179 pinctrl: pin-controller@58020000 {
180 compatible = "st,stm32-pinctrl";
181 #address-cells = <1>;
182 #size-cells = <1>;
186 compatible = "st,stm32-gpio";
187 gpio-controller;
188 #gpio-cells = <2>;
190 clocks = <&rcc STM32_CLOCK(AHB4, 0U)>;
194 compatible = "st,stm32-gpio";
195 gpio-controller;
196 #gpio-cells = <2>;
198 clocks = <&rcc STM32_CLOCK(AHB4, 1U)>;
202 compatible = "st,stm32-gpio";
203 gpio-controller;
204 #gpio-cells = <2>;
206 clocks = <&rcc STM32_CLOCK(AHB4, 2U)>;
210 compatible = "st,stm32-gpio";
211 gpio-controller;
212 #gpio-cells = <2>;
214 clocks = <&rcc STM32_CLOCK(AHB4, 3U)>;
218 compatible = "st,stm32-gpio";
219 gpio-controller;
220 #gpio-cells = <2>;
222 clocks = <&rcc STM32_CLOCK(AHB4, 4U)>;
226 compatible = "st,stm32-gpio";
227 gpio-controller;
228 #gpio-cells = <2>;
230 clocks = <&rcc STM32_CLOCK(AHB4, 5U)>;
234 compatible = "st,stm32-gpio";
235 gpio-controller;
236 #gpio-cells = <2>;
238 clocks = <&rcc STM32_CLOCK(AHB4, 6U)>;
242 compatible = "st,stm32-gpio";
243 gpio-controller;
244 #gpio-cells = <2>;
246 clocks = <&rcc STM32_CLOCK(AHB4, 7U)>;
250 compatible = "st,stm32-gpio";
251 gpio-controller;
252 #gpio-cells = <2>;
254 clocks = <&rcc STM32_CLOCK(AHB4, 8U)>;
258 compatible = "st,stm32-gpio";
259 gpio-controller;
260 #gpio-cells = <2>;
262 clocks = <&rcc STM32_CLOCK(AHB4, 9U)>;
266 compatible = "st,stm32-gpio";
267 gpio-controller;
268 #gpio-cells = <2>;
270 clocks = <&rcc STM32_CLOCK(AHB4, 10U)>;
275 compatible = "st,stm32-watchdog";
281 compatible = "st,stm32-window-watchdog";
283 clocks = <&rcc STM32_CLOCK(APB3, 6U)>;
289 compatible = "st,stm32-usart", "st,stm32-uart";
291 clocks = <&rcc STM32_CLOCK(APB2, 4U)>;
297 compatible = "st,stm32-usart", "st,stm32-uart";
299 clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
305 compatible = "st,stm32-usart", "st,stm32-uart";
307 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
313 compatible ="st,stm32-uart";
315 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
321 compatible = "st,stm32-uart";
323 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
329 compatible = "st,stm32-usart", "st,stm32-uart";
331 clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
337 compatible = "st,stm32-uart";
339 clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
345 compatible = "st,stm32-uart";
347 clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
354 compatible = "st,stm32-lpuart", "st,stm32-uart";
356 clocks = <&rcc STM32_CLOCK(APB4, 3U)>;
363 compatible = "st,stm32-rtc";
366 clocks = <&rcc STM32_CLOCK(APB4, 16U)>;
368 alarms-count = <2>;
369 alrm-exti-line = <17>;
374 compatible = "st,stm32-i2c-v2";
375 clock-frequency = <I2C_BITRATE_STANDARD>;
376 #address-cells = <1>;
377 #size-cells = <0>;
379 clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
381 interrupt-names = "event", "error";
386 compatible = "st,stm32-i2c-v2";
387 clock-frequency = <I2C_BITRATE_STANDARD>;
388 #address-cells = <1>;
389 #size-cells = <0>;
391 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
393 interrupt-names = "event", "error";
398 compatible = "st,stm32-i2c-v2";
399 clock-frequency = <I2C_BITRATE_STANDARD>;
400 #address-cells = <1>;
401 #size-cells = <0>;
403 clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
405 interrupt-names = "event", "error";
410 compatible = "st,stm32-i2c-v2";
411 clock-frequency = <I2C_BITRATE_STANDARD>;
412 #address-cells = <1>;
413 #size-cells = <0>;
415 clocks = <&rcc STM32_CLOCK(APB4, 7U)>;
417 interrupt-names = "event", "error";
422 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
423 #address-cells = <1>;
424 #size-cells = <0>;
426 clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
427 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
433 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
434 #address-cells = <1>;
435 #size-cells = <0>;
437 clocks = <&rcc STM32_CLOCK(APB1, 14U)>,
438 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
444 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
445 #address-cells = <1>;
446 #size-cells = <0>;
448 clocks = <&rcc STM32_CLOCK(APB1, 15U)>,
449 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
455 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
456 #address-cells = <1>;
457 #size-cells = <0>;
459 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
465 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
466 #address-cells = <1>;
467 #size-cells = <0>;
469 clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
475 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
476 #address-cells = <1>;
477 #size-cells = <0>;
479 clocks = <&rcc STM32_CLOCK(APB4, 5U)>;
485 compatible = "st,stm32h7-i2s", "st,stm32-i2s";
486 #address-cells = <1>;
487 #size-cells = <0>;
489 clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
490 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
493 dma-names = "tx", "rx";
499 compatible = "st,stm32h7-i2s", "st,stm32-i2s";
500 #address-cells = <1>;
501 #size-cells = <0>;
503 clocks = <&rcc STM32_CLOCK(APB1, 14U)>,
504 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
507 dma-names = "tx", "rx";
513 compatible = "st,stm32h7-i2s", "st,stm32-i2s";
514 #address-cells = <1>;
515 #size-cells = <0>;
517 clocks = <&rcc STM32_CLOCK(APB1, 15U)>,
518 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
521 dma-names = "tx", "rx";
527 compatible = "st,stm32h7-fdcan";
529 reg-names = "m_can", "message_ram";
530 clocks = <&rcc STM32_CLOCK(APB1_2, 8U)>;
532 interrupt-names = "int0", "int1", "calib";
533 bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
538 compatible = "st,stm32h7-fdcan";
540 reg-names = "m_can", "message_ram";
541 clocks = <&rcc STM32_CLOCK(APB1_2, 8U)>;
543 interrupt-names = "int0", "int1", "calib";
544 bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>;
549 compatible = "st,stm32-timers";
551 clocks = <&rcc STM32_CLOCK(APB2, 0U)>;
554 interrupt-names = "brk", "up", "trgcom", "cc";
559 compatible = "st,stm32-pwm";
561 #pwm-cells = <3>;
566 compatible = "st,stm32-timers";
568 clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
571 interrupt-names = "global";
576 compatible = "st,stm32-pwm";
578 #pwm-cells = <3>;
582 compatible = "st,stm32-counter";
588 compatible = "st,stm32-timers";
590 clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
593 interrupt-names = "global";
598 compatible = "st,stm32-pwm";
600 #pwm-cells = <3>;
604 compatible = "st,stm32-counter";
610 compatible = "st,stm32-timers";
612 clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
615 interrupt-names = "global";
620 compatible = "st,stm32-pwm";
622 #pwm-cells = <3>;
626 compatible = "st,stm32-counter";
632 compatible = "st,stm32-timers";
634 clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
637 interrupt-names = "global";
642 compatible = "st,stm32-pwm";
644 #pwm-cells = <3>;
648 compatible = "st,stm32-counter";
654 compatible = "st,stm32-timers";
656 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
659 interrupt-names = "global";
664 compatible = "st,stm32-counter";
670 compatible = "st,stm32-timers";
672 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
675 interrupt-names = "global";
680 compatible = "st,stm32-counter";
686 compatible = "st,stm32-timers";
688 clocks = <&rcc STM32_CLOCK(APB2, 1U)>;
691 interrupt-names = "brk", "up", "trgcom", "cc";
696 compatible = "st,stm32-pwm";
698 #pwm-cells = <3>;
703 compatible = "st,stm32-timers";
705 clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
708 interrupt-names = "global";
713 compatible = "st,stm32-pwm";
715 #pwm-cells = <3>;
719 compatible = "st,stm32-counter";
725 compatible = "st,stm32-timers";
727 clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
730 interrupt-names = "global";
735 compatible = "st,stm32-pwm";
737 #pwm-cells = <3>;
741 compatible = "st,stm32-counter";
747 compatible = "st,stm32-timers";
749 clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
752 interrupt-names = "global";
757 compatible = "st,stm32-pwm";
759 #pwm-cells = <3>;
763 compatible = "st,stm32-counter";
769 compatible = "st,stm32-timers";
771 clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
774 interrupt-names = "global";
779 compatible = "st,stm32-pwm";
781 #pwm-cells = <3>;
785 compatible = "st,stm32-counter";
791 compatible = "st,stm32-timers";
793 clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
796 interrupt-names = "global";
801 compatible = "st,stm32-pwm";
803 #pwm-cells = <3>;
807 compatible = "st,stm32-counter";
813 compatible = "st,stm32-timers";
815 clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
818 interrupt-names = "global";
823 compatible = "st,stm32-pwm";
825 #pwm-cells = <3>;
829 compatible = "st,stm32-counter";
835 compatible = "st,stm32-lptim";
836 clocks = <&rcc STM32_CLOCK(APB1, 9U)>;
837 #address-cells = <1>;
838 #size-cells = <0>;
841 interrupt-names = "wakeup";
853 compatible = "st,stm32-adc";
855 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
858 #io-channel-cells = <1>;
864 sampling-times = <2 3 9 17 33 65 388 811>;
865 st,adc-sequencer = "FULLY_CONFIGURABLE";
866 st,adc-oversampler = "OVERSAMPLER_EXTENDED";
870 compatible = "st,stm32-adc";
872 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
875 #io-channel-cells = <1>;
881 sampling-times = <2 3 9 17 33 65 388 811>;
882 st,adc-sequencer = "FULLY_CONFIGURABLE";
883 st,adc-oversampler = "OVERSAMPLER_EXTENDED";
888 compatible = "st,stm32-adc";
890 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
893 #io-channel-cells = <1>;
899 sampling-times = <2 3 9 17 33 65 388 811>;
900 st,adc-sequencer = "FULLY_CONFIGURABLE";
901 st,adc-oversampler = "OVERSAMPLER_EXTENDED";
905 compatible = "st,stm32-adc";
907 clocks = <&rcc STM32_CLOCK(AHB4, 24U)>;
910 #io-channel-cells = <1>;
916 sampling-times = <2 3 9 17 33 65 388 811>;
917 st,adc-sequencer = "FULLY_CONFIGURABLE";
918 st,adc-oversampler = "OVERSAMPLER_EXTENDED";
922 compatible = "st,stm32-dac";
924 clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
926 #io-channel-cells = <1>;
930 compatible = "st,stm32-dma-v1";
931 #dma-cells = <4>;
935 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
937 dma-offset = <0>;
938 dma-requests = <8>;
943 compatible = "st,stm32-dma-v1";
944 #dma-cells = <4>;
948 clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
950 dma-offset = <8>;
951 dma-requests = <8>;
956 compatible = "st,stm32-bdma";
957 #dma-cells = <4>;
961 clocks = <&rcc STM32_CLOCK(AHB4, 21U)>;
963 dma-offset = <0>;
964 dma-requests = <8>;
969 compatible = "st,stm32-dmamux";
970 #dma-cells = <3>;
974 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
975 dma-channels = <16>;
976 dma-generators = <8>;
979 * dma-requests is different among h7 socs,
985 compatible = "st,stm32-dmamux";
986 #dma-cells = <3>;
990 clocks = <&rcc STM32_CLOCK(AHB4, 21U)>;
991 dma-channels = <8>;
992 dma-generators = <8>;
995 * dma-requests is different among h7 socs,
1001 compatible = "st,stm32-rng";
1003 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
1009 compatible = "st,stm32-sdmmc";
1011 clocks = <&rcc STM32_CLOCK(AHB3, 16U)>,
1012 <&rcc STM32_SRC_PLL1_Q SDMMC_SEL(0)>;
1019 compatible = "st,stm32-sdmmc";
1021 clocks = <&rcc STM32_CLOCK(AHB2, 9U)>,
1022 <&rcc STM32_SRC_PLL1_Q SDMMC_SEL(0)>;
1029 compatible = "st,stm32h7-ethernet", "st,stm32-ethernet";
1032 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
1033 clocks = <&rcc STM32_CLOCK(AHB1, 15U)>,
1034 <&rcc STM32_CLOCK(AHB1, 16U)>,
1035 <&rcc STM32_CLOCK(AHB1, 17U)>;
1039 compatible = "st,stm32-mdio";
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1046 fmc: memory-controller@52004000 {
1047 compatible = "st,stm32h7-fmc";
1049 clocks = <&rcc STM32_CLOCK(AHB3, 12U)>;
1053 compatible = "st,stm32-fmc-sdram";
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1061 compatible = "zephyr,memory-region", "st,stm32-backup-sram";
1063 clocks = <&rcc STM32_CLOCK(AHB4, 28U)>;
1064 zephyr,memory-region = "BACKUP_SRAM";
1069 compatible = "st,stm32-qspi";
1070 #address-cells = <0x1>;
1071 #size-cells = <0x0>;
1074 clocks = <&rcc STM32_CLOCK(AHB3, 14U)>;
1079 compatible = "st,stm32-dcmi";
1082 interrupt-names = "dcmi";
1083 clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
1089 compatible = "st,stm32-temp-cal";
1090 ts-cal1-addr = <0x1FF1E820>;
1091 ts-cal2-addr = <0x1FF1E840>;
1092 ts-cal1-temp = <30>;
1093 ts-cal2-temp = <110>;
1094 ts-cal-vrefanalog = <3300>;
1095 ts-cal-resolution = <16>;
1096 io-channels = <&adc3 18>;
1101 compatible = "st,stm32-vbat";
1107 compatible = "st,stm32-vref";
1108 vrefint-cal-addr = <0x1FF1E860>;
1109 vrefint-cal-mv = <3300>;
1114 compatible = "st,stm32-smbus";
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1122 compatible = "st,stm32-smbus";
1123 #address-cells = <1>;
1124 #size-cells = <0>;
1130 compatible = "st,stm32-smbus";
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1138 compatible = "st,stm32-smbus";
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1147 arm,num-irq-priority-bits = <4>;