Lines Matching +full:stm32 +full:- +full:rcc
2 * Copyright (c) 2017 Florian Vaussard, HEIG-VD
4 * SPDX-License-Identifier: Apache-2.0
9 /delete-node/ &dac1;
10 /delete-node/ &rng;
15 #clock-cells = <0>;
16 compatible = "st,stm32f411-plli2s-clock";
21 #clock-cells = <0>;
22 compatible = "st,stm32-clock-mux";
23 clocks = <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
29 compatible = "st,stm32f412", "st,stm32f4", "simple-bus";
31 pinctrl: pin-controller@40020000 {
35 compatible = "st,stm32-gpio";
36 gpio-controller;
37 #gpio-cells = <2>;
39 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
43 compatible = "st,stm32-gpio";
44 gpio-controller;
45 #gpio-cells = <2>;
47 clocks = <&rcc STM32_CLOCK(AHB1, 6U)>;
52 compatible = "st,stm32-usart", "st,stm32-uart";
54 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
61 compatible = "st,stm32-spi";
62 #address-cells = <1>;
63 #size-cells = <0>;
65 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
71 compatible = "st,stm32-spi";
72 #address-cells = <1>;
73 #size-cells = <0>;
75 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
81 compatible = "st,stm32-i2s";
82 #address-cells = <1>;
83 #size-cells = <0>;
85 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
89 dma-names = "tx", "rx";
94 compatible = "st,stm32-timers";
96 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
99 interrupt-names = "global";
104 compatible = "st,stm32-counter";
110 compatible = "st,stm32-timers";
112 clocks = <&rcc STM32_CLOCK(APB2, 1U)>;
115 interrupt-names = "brk", "up", "trgcom", "cc";
120 compatible = "st,stm32-pwm";
122 #pwm-cells = <3>;
126 compatible = "st,stm32-qdec";
128 st,input-filter-level = <NO_FILTER>;
133 compatible = "st,stm32-timers";
135 clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
138 interrupt-names = "global";
143 compatible = "st,stm32-pwm";
145 #pwm-cells = <3>;
149 compatible = "st,stm32-counter";
155 compatible = "st,stm32-timers";
157 clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
160 interrupt-names = "global";
165 compatible = "st,stm32-pwm";
167 #pwm-cells = <3>;
171 compatible = "st,stm32-counter";
177 compatible = "st,stm32-timers";
179 clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
182 interrupt-names = "global";
187 compatible = "st,stm32-pwm";
189 #pwm-cells = <3>;
193 compatible = "st,stm32-counter";
199 compatible = "st,stm32-rng";
202 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
207 num-bidir-endpoints = <6>;
211 clocks = <&rcc STM32_CLOCK(APB2, 11U)>,
212 <&rcc STM32_SRC_CK48 SDIO_SEL(0)>;
216 compatible = "st,stm32-qspi";
217 #address-cells = <0x1>;
218 #size-cells = <0x0>;
221 clocks = <&rcc STM32_CLOCK(AHB3, 1U)>;
226 compatible = "st,stm32-bxcan";
229 interrupt-names = "TX", "RX0", "RX1", "SCE";
230 clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
235 compatible = "st,stm32-bxcan";
238 interrupt-names = "TX", "RX0", "RX1", "SCE";
240 clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
241 master-can-reg = <0x40006400>;
247 io-channels = <&adc1 18>;