Lines Matching +full:stm32 +full:- +full:rcc
6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32f4_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32f4_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32f2_4_7_reset.h>
18 #include <zephyr/dt-bindings/adc/adc.h>
24 zephyr,flash-controller = &flash;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 compatible = "arm,cortex-m3";
39 compatible = "mmio-sram";
43 clk_hse: clk-hse {
44 #clock-cells = <0>;
45 compatible = "st,stm32-hse-clock";
49 clk_hsi: clk-hsi {
50 #clock-cells = <0>;
51 compatible = "fixed-clock";
52 clock-frequency = <DT_FREQ_M(16)>;
56 clk_lse: clk-lse {
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <32768>;
63 clk_lsi: clk-lsi {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <DT_FREQ_K(32)>;
71 #clock-cells = <0>;
72 compatible = "st,stm32f2-pll-clock";
78 flash: flash-controller@40023c00 {
79 compatible = "st,stm32-flash-controller", "st,stm32f2-flash-controller";
83 #address-cells = <1>;
84 #size-cells = <1>;
87 compatible = "st,stm32-nv-flash", "soc-nv-flash";
89 write-block-size = <1>;
91 max-erase-time = <4000>;
95 rcc: rcc@40023800 { label
96 compatible = "st,stm32-rcc";
97 #clock-cells = <2>;
100 rctl: reset-controller {
101 compatible = "st,stm32-rcc-rctl";
102 #reset-cells = <1>;
106 exti: interrupt-controller@40013c00 {
107 compatible = "st,stm32-exti";
108 interrupt-controller;
109 #interrupt-cells = <1>;
110 #address-cells = <1>;
112 num-lines = <16>;
115 interrupt-names = "line0", "line1", "line2", "line3",
116 "line4", "line5-9", "line10-15";
117 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
121 pinctrl: pin-controller@40020000 {
122 compatible = "st,stm32-pinctrl";
123 #address-cells = <1>;
124 #size-cells = <1>;
128 compatible = "st,stm32-gpio";
129 gpio-controller;
130 #gpio-cells = <2>;
132 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
136 compatible = "st,stm32-gpio";
137 gpio-controller;
138 #gpio-cells = <2>;
140 clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
144 compatible = "st,stm32-gpio";
145 gpio-controller;
146 #gpio-cells = <2>;
148 clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
152 compatible = "st,stm32-gpio";
153 gpio-controller;
154 #gpio-cells = <2>;
156 clocks = <&rcc STM32_CLOCK(AHB1, 3U)>;
160 compatible = "st,stm32-gpio";
161 gpio-controller;
162 #gpio-cells = <2>;
164 clocks = <&rcc STM32_CLOCK(AHB1, 4U)>;
168 compatible = "st,stm32-gpio";
169 gpio-controller;
170 #gpio-cells = <2>;
172 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
176 compatible = "st,stm32-gpio";
177 gpio-controller;
178 #gpio-cells = <2>;
180 clocks = <&rcc STM32_CLOCK(AHB1, 6U)>;
184 compatible = "st,stm32-gpio";
185 gpio-controller;
186 #gpio-cells = <2>;
188 clocks = <&rcc STM32_CLOCK(AHB1, 7U)>;
192 compatible = "st,stm32-gpio";
193 gpio-controller;
194 #gpio-cells = <2>;
196 clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;
201 compatible = "st,stm32-rtc";
203 clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
206 alarms-count = <2>;
207 alrm-exti-line = <17>;
211 compatible = "st,stm32-bbram";
212 st,backup-regs = <20>;
218 compatible = "st,stm32-watchdog";
224 compatible = "st,stm32-window-watchdog";
226 clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
232 compatible = "st,stm32-usart", "st,stm32-uart";
234 clocks = <&rcc STM32_CLOCK(APB2, 4U)>;
241 compatible = "st,stm32-usart", "st,stm32-uart";
243 clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
250 compatible = "st,stm32-usart", "st,stm32-uart";
252 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
259 compatible = "st,stm32-usart", "st,stm32-uart";
261 clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
268 compatible ="st,stm32-uart";
270 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
277 compatible = "st,stm32-uart";
279 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
286 compatible = "st,stm32-spi";
287 #address-cells = <1>;
288 #size-cells = <0>;
290 clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
296 compatible = "st,stm32-spi";
297 #address-cells = <1>;
298 #size-cells = <0>;
300 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
306 compatible = "st,stm32-spi";
307 #address-cells = <1>;
308 #size-cells = <0>;
310 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
316 compatible = "st,stm32-i2c-v1";
317 clock-frequency = <I2C_BITRATE_STANDARD>;
318 #address-cells = <1>;
319 #size-cells = <0>;
321 clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
323 interrupt-names = "event", "error";
328 compatible = "st,stm32-i2c-v1";
329 clock-frequency = <I2C_BITRATE_STANDARD>;
330 #address-cells = <1>;
331 #size-cells = <0>;
333 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
335 interrupt-names = "event", "error";
340 compatible = "st,stm32-i2c-v1";
341 clock-frequency = <I2C_BITRATE_STANDARD>;
342 #address-cells = <1>;
343 #size-cells = <0>;
345 clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
347 interrupt-names = "event", "error";
352 compatible = "st,stm32-otgfs";
355 interrupt-names = "otgfs";
356 num-bidir-endpoints = <4>;
357 ram-size = <1280>;
358 maximum-speed = "full-speed";
359 clocks = <&rcc STM32_CLOCK(AHB2, 7U)>,
360 <&rcc STM32_SRC_PLL_Q NO_SEL>;
366 compatible = "st,stm32f4-adc", "st,stm32-adc";
368 clocks = <&rcc STM32_CLOCK(APB2, 8U)>;
371 #io-channel-cells = <1>;
376 sampling-times = <3 15 28 58 84 112 144 480>;
377 st,adc-clock-source = "SYNC";
378 st,adc-sequencer = "FULLY_CONFIGURABLE";
379 st,adc-oversampler = "OVERSAMPLER_NONE";
383 compatible = "st,stm32-dma-v1";
384 #dma-cells = <4>;
387 clocks = <&rcc STM32_CLOCK(AHB1, 21U)>;
392 compatible = "st,stm32-dma-v1";
393 #dma-cells = <4>;
396 clocks = <&rcc STM32_CLOCK(AHB1, 22U)>;
402 compatible = "st,stm32-dac";
404 clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
406 #io-channel-cells = <1>;
410 compatible = "st,stm32-timers";
412 clocks = <&rcc STM32_CLOCK(APB2, 0U)>;
415 interrupt-names = "brk", "up", "trgcom", "cc";
420 compatible = "st,stm32-pwm";
422 #pwm-cells = <3>;
427 compatible = "st,stm32-timers";
429 clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
432 interrupt-names = "global";
437 compatible = "st,stm32-pwm";
439 #pwm-cells = <3>;
444 compatible = "st,stm32-timers";
446 clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
449 interrupt-names = "global";
454 compatible = "st,stm32-pwm";
456 #pwm-cells = <3>;
460 compatible = "st,stm32-counter";
466 compatible = "st,stm32-timers";
468 clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
471 interrupt-names = "global";
476 compatible = "st,stm32-pwm";
478 #pwm-cells = <3>;
482 compatible = "st,stm32-counter";
488 compatible = "st,stm32-timers";
490 clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
493 interrupt-names = "global";
498 compatible = "st,stm32-pwm";
500 #pwm-cells = <3>;
504 compatible = "st,stm32-counter";
510 compatible = "st,stm32-timers";
512 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
515 interrupt-names = "global";
520 compatible = "st,stm32-counter";
526 compatible = "st,stm32-timers";
528 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
531 interrupt-names = "global";
536 compatible = "st,stm32-counter";
542 compatible = "st,stm32-timers";
544 clocks = <&rcc STM32_CLOCK(APB2, 1U)>;
547 interrupt-names = "brk", "up", "trgcom", "cc";
552 compatible = "st,stm32-pwm";
554 #pwm-cells = <3>;
559 compatible = "st,stm32-timers";
561 clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
564 interrupt-names = "global";
569 compatible = "st,stm32-pwm";
571 #pwm-cells = <3>;
575 compatible = "st,stm32-counter";
581 compatible = "st,stm32-timers";
583 clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
586 interrupt-names = "global";
591 compatible = "st,stm32-pwm";
593 #pwm-cells = <3>;
597 compatible = "st,stm32-counter";
603 compatible = "st,stm32-timers";
605 clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
608 interrupt-names = "global";
613 compatible = "st,stm32-pwm";
615 #pwm-cells = <3>;
619 compatible = "st,stm32-counter";
625 compatible = "st,stm32-timers";
627 clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
630 interrupt-names = "global";
635 compatible = "st,stm32-pwm";
637 #pwm-cells = <3>;
641 compatible = "st,stm32-counter";
647 compatible = "st,stm32-timers";
649 clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
652 interrupt-names = "global";
657 compatible = "st,stm32-pwm";
659 #pwm-cells = <3>;
663 compatible = "st,stm32-counter";
669 compatible = "st,stm32-timers";
671 clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
674 interrupt-names = "global";
679 compatible = "st,stm32-pwm";
681 #pwm-cells = <3>;
685 compatible = "st,stm32-counter";
691 compatible = "st,stm32-rng";
694 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
699 compatible = "zephyr,memory-region", "st,stm32-backup-sram";
701 clocks = <&rcc STM32_CLOCK(AHB1, 18U)>;
702 zephyr,memory-region = "BACKUP_SRAM";
708 compatible = "st,stm32-temp";
709 io-channels = <&adc1 16>;
716 compatible = "usb-nop-xceiv";
717 #phy-cells = <0>;
721 compatible = "st,stm32-smbus";
722 #address-cells = <1>;
723 #size-cells = <0>;
729 compatible = "st,stm32-smbus";
730 #address-cells = <1>;
731 #size-cells = <0>;
737 compatible = "st,stm32-smbus";
738 #address-cells = <1>;
739 #size-cells = <0>;
746 arm,num-irq-priority-bits = <4>;