Lines Matching +full:0 +full:x18
17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0>;
29 reg = <0xe000ed90 0x40>;
37 reg = <0x41030000 DT_SIZE_K(64)>;
52 #size-cells = <0>;
55 gpio0: gpio@0 {
60 reg = <0x0>;
69 reg = <0x1000>;
78 reg = <0x1100>;
87 reg = <0x1200>;
96 reg = <0x1300>;
105 reg = <0x100>;
114 reg = <0x200>;
123 reg = <0x1400>;
132 reg = <0x1500>;
141 reg = <0x1600>;
150 reg = <0x1700>;
159 reg = <0x300>;
168 reg = <0x400>;
177 reg = <0x500>;
186 reg = <0x600>;
195 reg = <0x700>;
204 reg = <0x800>;
213 reg = <0x900>;
222 reg = <0xA00>;
230 channel = <0>;
231 reg = <0x4004b800 0x18>;
239 reg = <0x4004bc00 0x18>;
247 reg = <0x4004c000 0x18>;
255 reg = <0x4004c400 0x18>;
263 reg = <0x4004c800 0x18>;
271 reg = <0x4004e000 0x18>;