Lines Matching +full:clock +full:- +full:names
4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/ra_clock.h>
8 #include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
13 compatible = "mmio-sram";
17 flash-controller@407e0000 {
18 block-32kb-linear-end = <21>;
20 compatible = "renesas,ra-nv-flash";
22 write-block-size = <128>;
23 erase-block-size = <8192>;
24 renesas,programming-enable;
28 compatible = "renesas,ra-nv-flash";
30 write-block-size = <4>;
31 erase-block-size = <64>;
32 renesas,programming-enable;
37 compatible = "renesas,ra-sce7-rng";
42 channel-available-mask = <0x1700ef>;
46 channel-available-mask = <0x300e7>;
51 #address-cells = <1>;
52 #size-cells = <1>;
54 xtal: clock-main-osc {
55 compatible = "renesas,ra-cgc-external-clock";
56 clock-frequency = <DT_FREQ_M(12)>;
57 #clock-cells = <0>;
61 hoco: clock-hoco {
62 compatible = "fixed-clock";
63 clock-frequency = <DT_FREQ_M(20)>;
64 #clock-cells = <0>;
67 moco: clock-moco {
68 compatible = "fixed-clock";
69 clock-frequency = <DT_FREQ_M(8)>;
70 #clock-cells = <0>;
73 loco: clock-loco {
74 compatible = "fixed-clock";
75 clock-frequency = <32768>;
76 #clock-cells = <0>;
79 subclk: clock-subclk {
80 compatible = "renesas,ra-cgc-subclk";
81 clock-frequency = <32768>;
82 #clock-cells = <0>;
87 compatible = "renesas,ra-cgc-pll";
88 #clock-cells = <0>;
98 compatible = "renesas,ra-cgc-pclk-block";
101 reg-names = "MSTPA", "MSTPB","MSTPC",
103 #clock-cells = <0>;
108 compatible = "renesas,ra-cgc-pclk";
109 clock-frequency = <120000000>;
111 #clock-cells = <2>;
116 compatible = "renesas,ra-cgc-pclk";
118 #clock-cells = <2>;
123 compatible = "renesas,ra-cgc-pclk";
125 #clock-cells = <2>;
130 compatible = "renesas,ra-cgc-pclk";
132 #clock-cells = <2>;
137 compatible = "renesas,ra-cgc-pclk";
139 #clock-cells = <2>;
144 compatible = "renesas,ra-cgc-pclk";
147 compatible = "renesas,ra-cgc-busclk";
148 clk-out-div = <2>;
150 #clock-cells = <0>;
152 #clock-cells = <2>;
157 compatible = "renesas,ra-cgc-pclk";
159 #clock-cells = <2>;
164 compatible = "renesas,ra-cgc-pclk";
166 #clock-cells = <2>;
171 compatible = "renesas,ra-cgc-pclk";
172 #clock-cells = <2>;
180 port-irqs = <&port_irq6 &port_irq7 &port_irq8
183 port-irq-names = "port-irq6",
184 "port-irq7",
185 "port-irq8",
186 "port-irq9",
187 "port-irq10",
188 "port-irq11",
189 "port-irq12",
190 "port-irq13";
191 port-irq6-pins = <0>;
192 port-irq7-pins = <1>;
193 port-irq8-pins = <2>;
194 port-irq9-pins = <4>;
195 port-irq10-pins = <5>;
196 port-irq11-pins = <6>;
197 port-irq12-pins = <8>;
198 port-irq13-pins = <15>;
202 port-irqs = <&port_irq0 &port_irq1 &port_irq2
204 port-irq-names = "port-irq0",
205 "port-irq1",
206 "port-irq2",
207 "port-irq3",
208 "port-irq4";
209 port-irq0-pins = <5>;
210 port-irq1-pins = <1 4>;
211 port-irq2-pins = <0>;
212 port-irq3-pins = <10>;
213 port-irq4-pins = <11>;
217 port-irqs = <&port_irq0 &port_irq1 &port_irq2
219 port-irq-names = "port-irq0",
220 "port-irq1",
221 "port-irq2",
222 "port-irq3";
223 port-irq0-pins = <6>;
224 port-irq1-pins = <5>;
225 port-irq2-pins = <13>;
226 port-irq3-pins = <12>;
230 port-irqs = <&port_irq5 &port_irq6
232 port-irq-names = "port-irq5",
233 "port-irq6",
234 "port-irq8",
235 "port-irq9";
236 port-irq5-pins = <2>;
237 port-irq6-pins = <1>;
238 port-irq8-pins = <5>;
239 port-irq9-pins = <4>;
243 port-irqs = <&port_irq0 &port_irq4 &port_irq5
246 port-irq-names = "port-irq0",
247 "port-irq4",
248 "port-irq5",
249 "port-irq6",
250 "port-irq7",
251 "port-irq8",
252 "port-irq9";
253 port-irq0-pins = <0>;
254 port-irq4-pins = <2 11>;
255 port-irq5-pins = <1 10>;
256 port-irq6-pins = <9>;
257 port-irq7-pins = <8>;
258 port-irq8-pins = <15>;
259 port-irq9-pins = <14>;
263 port-irqs = <&port_irq11 &port_irq12>;
264 port-irq-names = "port-irq11",
265 "port-irq12";
266 port-irq11-pins = <1>;
267 port-irq12-pins = <2>;
271 port-irqs = <&port_irq11>;
272 port-irq-names = "port-irq11";
273 port-irq11-pins = <8>;
277 has-output-amplifier;