Lines Matching +full:clock +full:- +full:frequency
3 * Copyright (c) 2024-2025 Renesas Electronics Corporation
7 * SPDX-License-Identifier: Apache-2.0
13 #address-cells = <1>;
14 #size-cells = <1>;
16 xtal: clock-main-osc {
17 compatible = "renesas,ra-cgc-external-clock";
18 clock-frequency = <DT_FREQ_M(20)>;
19 #clock-cells = <0>;
23 hoco: clock-hoco {
24 compatible = "fixed-clock";
25 clock-frequency = <DT_FREQ_M(48)>;
26 #clock-cells = <0>;
29 moco: clock-moco {
30 compatible = "fixed-clock";
31 clock-frequency = <DT_FREQ_M(8)>;
32 #clock-cells = <0>;
35 loco: clock-loco {
36 compatible = "fixed-clock";
37 clock-frequency = <32768>;
38 #clock-cells = <0>;
41 subclk: clock-subclk {
42 compatible = "renesas,ra-cgc-subclk";
43 clock-frequency = <32768>;
44 #clock-cells = <0>;
49 compatible = "renesas,ra-cgc-pclk-block";
52 reg-names = "MSTPA", "MSTPB","MSTPC",
54 #clock-cells = <0>;
59 compatible = "renesas,ra-cgc-pclk";
60 clock-frequency = <48000000>;
62 #clock-cells = <2>;
67 compatible = "renesas,ra-cgc-pclk";
69 #clock-cells = <2>;
74 compatible = "renesas,ra-cgc-pclk";
76 #clock-cells = <2>;
81 compatible = "renesas,ra-cgc-pclk";
82 #clock-cells = <2>;