Lines Matching +full:0 +full:x401d8000
24 #size-cells = <0>;
26 cpu0: cpu@0 {
30 reg = <0>;
37 reg = <0xe000ed90 0x40>;
42 reg = <0xe0000000 0x1000>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
85 #clock-cells = <0>;
91 reg = <0x400b0000 0x4000>;
92 interrupts = <38 0>;
101 itcm: itcm@0 {
103 reg = <0x00000000 DT_SIZE_K(128)>;
109 reg = <0x20000000 DT_SIZE_K(128)>;
115 reg = <0x20200000 DT_SIZE_K(256)>;
122 reg = <0x402a8000 0x4000>;
123 interrupts = <108 0>;
125 #size-cells = <0>;
129 clocks = <&ccm IMX_CCM_FLEXSPI_CLK 0x0 0x0>;
134 reg = <0x402a4000 0x4000>;
135 interrupts = <107 0>;
137 #size-cells = <0>;
141 clocks = <&ccm IMX_CCM_FLEXSPI2_CLK 0x0 0x0>;
146 reg = <0x402f0000 0x4000>;
147 interrupts = <109 0>;
155 reg = <0x401ec000 0x4000>;
156 interrupts = <100 0>;
162 reg = <0x401f0000 0x4000>;
163 interrupts = <101 0>;
165 clocks = <&ccm IMX_CCM_GPT_CLK 0x68 24>;
170 reg = <0x401dc000 0x7a>;
171 interrupts = <133 0>;
172 clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
175 channel = <0>;
197 reg = <0x401e0000 0x7a>;
198 interrupts = <134 0>;
199 clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
202 channel = <0>;
224 reg = <0x401e4000 0x7a>;
225 interrupts = <135 0>;
226 clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
229 channel = <0>;
251 reg = <0x401e8000 0x7a>;
252 interrupts = <136 0>;
253 clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
256 channel = <0>;
278 reg = <0x400fc000 0x4000>;
285 #clock-cells = <0>;
291 #clock-cells = <0>;
297 #clock-cells = <0>;
303 numerator = <0>;
305 src = <0>;
306 #clock-cells = <0>;
314 reg = <0x400d4000 0x4000>;
318 interrupts = <46 0>;
324 reg = <0x401b8000 0x4000>;
325 interrupts = <80 0>, <81 0>;
332 reg = <0x401bc000 0x4000>;
333 interrupts = <82 0>, <83 0>;
340 reg = <0x401c0000 0x4000>;
341 interrupts = <84 0>, <85 0>;
348 reg = <0x401c4000 0x4000>;
349 interrupts = <86 0>, <87 0>;
356 reg = <0x400c0000 0x4000>;
357 interrupts = <88 0>, <89 0>;
367 reg = <0x42000000 0x4000>;
374 reg = <0x42004000 0x4000>;
381 reg = <0x42008000 0x4000>;
388 reg = <0x4200c000 0x4000>;
397 #size-cells = <0>;
398 reg = <0x403f0000 0x4000>;
399 interrupts = <28 0>;
400 clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 6>;
408 #size-cells = <0>;
409 reg = <0x403f4000 0x4000>;
410 interrupts = <29 0>;
411 clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 8>;
419 #size-cells = <0>;
420 reg = <0x403f8000 0x4000>;
421 interrupts = <30 0>;
422 clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 10>;
430 #size-cells = <0>;
431 reg = <0x403fc000 0x4000>;
432 interrupts = <31 0>;
433 clocks = <&ccm IMX_CCM_LPI2C_CLK 0x80 24>;
439 reg = <0x401f8000 0x4000>;
449 reg = <0x402b8000 0x4000>;
450 interrupts = <42 0>;
457 reg = <0x40394000 0x4000>;
460 clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 0>;
462 #size-cells = <0>;
467 reg = <0x40398000 0x4000>;
470 clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 2>;
472 #size-cells = <0>;
477 reg = <0x4039c000 0x4000>;
480 clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 4>;
482 #size-cells = <0>;
487 reg = <0x403a0000 0x4000>;
490 clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 6>;
492 #size-cells = <0>;
497 reg = <0x40184000 0x4000>;
498 interrupts = <20 0>;
499 clocks = <&ccm IMX_CCM_LPUART_CLK 0x7c 24>;
507 reg = <0x40188000 0x4000>;
508 interrupts = <21 0>;
509 clocks = <&ccm IMX_CCM_LPUART_CLK 0x68 28>;
517 reg = <0x4018c000 0x4000>;
518 interrupts = <22 0>;
519 clocks = <&ccm IMX_CCM_LPUART_CLK 0x68 12>;
527 reg = <0x40190000 0x4000>;
528 interrupts = <23 0>;
529 clocks = <&ccm IMX_CCM_LPUART_CLK 0x6c 24>;
537 reg = <0x40194000 0x4000>;
538 interrupts = <24 0>;
539 clocks = <&ccm IMX_CCM_LPUART_CLK 0x74 2>;
547 reg = <0x40198000 0x4000>;
548 interrupts = <25 0>;
549 clocks = <&ccm IMX_CCM_LPUART_CLK 0x74 6>;
557 reg = <0x4019c000 0x4000>;
558 interrupts = <26 0>;
559 clocks = <&ccm IMX_CCM_LPUART_CLK 0x7c 26>;
567 reg = <0x401a0000 0x4000>;
568 interrupts = <27 0>;
569 clocks = <&ccm IMX_CCM_LPUART_CLK 0x80 14>;
577 reg = <0x400C4000 0x1000>;
578 interrupts = <67 0>;
580 sample-period-mode = <0>;
587 reg = <0x400C8000 0x1000>;
588 interrupts = <68 0>;
590 sample-period-mode = <0>;
597 reg = <0x403dc000 0x4000>;
598 interrupts = <106 0>;
602 index = <0>;
603 interrupts = <102 0>;
605 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
613 interrupts = <103 0>;
615 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
623 interrupts = <104 0>;
625 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
633 interrupts = <105 0>;
635 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
643 reg = <0x403e0000 0x4000>;
644 interrupts = <141 0>;
648 index = <0>;
649 interrupts = <137 0>;
651 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
659 interrupts = <138 0>;
661 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
669 interrupts = <139 0>;
671 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
679 interrupts = <140 0>;
681 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
689 reg = <0x403e4000 0x4000>;
690 interrupts = <146 0>;
694 index = <0>;
695 interrupts = <142 0>;
697 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
705 interrupts = <143 0>;
707 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
715 interrupts = <144 0>;
717 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
725 interrupts = <145 0>;
727 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
735 reg = <0x403e8000 0x4000>;
736 interrupts = <151 0>;
740 index = <0>;
741 interrupts = <147 0>;
743 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
751 interrupts = <148 0>;
753 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
761 interrupts = <149 0>;
763 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
771 interrupts = <150 0>;
773 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
781 reg = <0x402D8000 0x628>;
782 clocks = <&ccm IMX_CCM_ENET_CLK 0 0>;
785 interrupts = <114 0>;
795 #size-cells = <0>;
799 interrupts = <115 0>;
801 clocks = <&ccm IMX_CCM_ENET_PLL 0 0>;
807 reg = <0x400f8000 0x4000>;
813 reg = <0x400cc000 0x4000>;
815 interrupts = <53 0>;
820 reg = <0x402E0000 0x200>;
830 reg = <0x402E0200 0x200>;
840 reg = <0x400D9000 0x1000>;
846 reg = <0x400DA000 0x1000>;
852 reg = <0x402c0000 0x4000>;
854 interrupts = <110 0>;
855 clocks = <&ccm IMX_CCM_USDHC1_CLK 0 0>;
864 reg = <0x402c4000 0x4000>;
866 interrupts = <111 0>;
867 clocks = <&ccm IMX_CCM_USDHC2_CLK 0 0>;
876 reg = <0x402BC000 0x4000>;
889 reg = <0x400E8000 0x4000>,
890 <0x400EC000 0x4000>;
891 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
892 <4 0>, <5 0>, <6 0>, <7 0>,
893 <8 0>, <9 0>, <10 0>, <11 0>,
894 <12 0>, <13 0>, <14 0>, <15 0>,
895 <16 0>;
897 clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
903 reg = <0x401d0000 0x1000>;
904 interrupts = <36 0>;
906 clocks = <&ccm IMX_CCM_CAN_CLK 0x68 14>;
913 reg = <0x401d4000 0x1000>;
914 interrupts = <37 0>;
916 clocks = <&ccm IMX_CCM_CAN_CLK 0x68 18>;
923 reg = <0x401d8000 0x1000>;
924 interrupts = <154 0>;
926 clocks = <&ccm IMX_CCM_CAN_CLK 0x84 6>;
933 reg = <0x400b8000 0xA>;
935 interrupts = <92 0>;
940 reg = <0x400d0000 0xA>;
942 interrupts = <45 0>;
947 reg = <0x400d8000 0x4000>;
954 reg = <0x400AC000 0x4000>;
960 reg = <0x402b4000 0x4000>;
961 interrupts = <44 0>;
963 #dma-cells = <0>;
969 #size-cells = <0>;
971 reg = <0x40384000 0x4000>;
972 clocks = <&ccm IMX_CCM_SAI1_CLK 0x7C 18>;
979 pll-clocks = <&anatop 0x70 0xC000 0>,
980 <&anatop 0x70 0x7F 32>,
981 <&anatop 0x70 0x180000 1>,
982 <&anatop 0x80 0x3FFFFFFF 77>,
983 <&anatop 0x90 0x3FFFFFFF 100>;
988 * A pre-div value of 0x1 results in a pre-divider of
991 pre-div = <0x3>;
992 podf = <0x0F>;
993 pinmuxes = <&iomuxcgpr 0x4 0x80000>;
994 interrupts = <56 0>;
995 dmas = <&edma0 0 19>, <&edma0 0 20>;
998 * cannot be 0
1001 nxp,tx-dma-channel = <0>;
1009 #size-cells = <0>;
1011 reg = <0x40388000 0x4000>;
1012 clocks = <&ccm IMX_CCM_SAI2_CLK 0x7C 20>;
1015 pre-div = <0>;
1017 pll-clocks = <&anatop 0x70 0xC000 0x0>,
1018 <&anatop 0x70 0x7F 32>,
1019 <&anatop 0x70 0x180000 1>,
1020 <&anatop 0x80 0x3FFFFFFF 77>,
1021 <&anatop 0x90 0x3FFFFFFF 100>;
1023 pinmuxes = <&iomuxcgpr 0x4 0x100000>;
1024 interrupts = <57 0>;
1025 dmas = <&edma0 0 21>, <&edma0 0 22>;
1027 nxp,tx-channel = <0>;
1036 #size-cells = <0>;
1038 reg = <0x4038C000 0x4000>;
1039 clocks = <&ccm IMX_CCM_SAI3_CLK 0x7C 22>;
1042 pre-div = <0>;
1044 pll-clocks = <&anatop 0x70 0xC000 0>,
1045 <&anatop 0x70 0x7F 32>,
1046 <&anatop 0x70 0x180000 1>,
1047 <&anatop 0x80 0x3FFFFFFF 77>,
1048 <&anatop 0x90 0x3FFFFFFF 100>;
1050 pinmuxes = <&iomuxcgpr 0x4 0x200000>;
1051 interrupts = <58 0>, <59 0>;
1052 dmas = <&edma0 0 83>, <&edma0 0 84>;
1054 nxp,tx-channel = <0>;
1062 reg = <0x403c8000 0x4000>;
1063 interrupts = <129 0>;
1069 reg = <0x403cc000 0x4000>;
1070 interrupts = <130 0>;
1076 reg = <0x403d0000 0x4000>;
1077 interrupts = <131 0>;
1083 reg = <0x403d4000 0x4000>;
1084 interrupts = <132 0>;
1090 reg = <0x403bc000 0x4000>;
1091 interrupts = <116 0>, <117 0>;
1097 reg = <0x403c0000 0x4000>;
1103 reg = <0x403c4000 0x4000>;
1109 reg = <0x402fc000 0x4000>;
1110 interrupts = <50 0>, <51 0>;
1116 reg = <0x400d8000 0x2a0>;
1122 reg = <0x40084000 0x1000>;
1123 clocks = <&ccm IMX_CCM_PIT_CLK 0x0 0>;
1124 interrupts = <122 0>;
1125 max-load-value = <0xffffffff>;
1128 #size-cells = <0>;
1130 pit0_channel0: pit0_channel@0 {
1132 reg = <0>;
1157 reg = <0x401ac000 0x4000>;
1159 interrupts = <90 0>;
1160 clocks = <&ccm IMX_CCM_FLEXIO1_CLK 0 0>;