Lines Matching +full:0 +full:x70
23 reg = <0x00000000 DT_SIZE_K(32)>;
27 reg = <0x20000000 DT_SIZE_K(32)>;
31 reg = <0x20200000 DT_SIZE_K(64)>;
43 interrupts = <70 0>, <71 0>;
47 interrupts = <73 0>;
51 interrupts = <30 0>;
55 interrupts = <31 0>;
61 irq-shared-offset = <0>;
80 reg = <0x42000000 0x4000>;
81 interrupts = <72 0>;
110 reg = <0x400a0000 0x4000>;
111 interrupts = <26 0>;
113 #size-cells = <0>;
117 clocks = <&ccm IMX_CCM_FLEXSPI_CLK 0x0 0x0>;
131 #size-cells = <0>;
132 reg = <0x401a4000 0x4000>;
133 interrupts = <28 0>;
134 clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 6>;
142 #size-cells = <0>;
143 reg = <0x401a8000 0x4000>;
144 interrupts = <29 0>;
145 clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 8>;
161 reg = <0x40194000 0x4000>;
164 clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 0>;
166 #size-cells = <0>;
171 reg = <0x40198000 0x4000>;
174 clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 2>;
176 #size-cells = <0>;
195 reg = <0x401cc000 0x4000>;
196 interrupts = <38 0>;
200 index = <0>;
201 interrupts = <34 0>;
203 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
211 interrupts = <35 0>;
213 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
221 interrupts = <36 0>;
223 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
231 interrupts = <37 0>;
233 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
250 reg = <0x400e4000 0x200>;
282 #size-cells = <0>;
284 reg = <0x401e0000 0x4000>;
285 clocks = <&ccm IMX_CCM_SAI1_CLK 0x7C 18>;
292 pll-clocks = <&anatop 0x70 0xC000 0>,
293 <&anatop 0x70 0x7F 32>,
294 <&anatop 0x70 0x180000 1>,
295 <&anatop 0x80 0x3FFFFFFF 77>,
296 <&anatop 0x90 0x3FFFFFFF 100>;
301 * A pre-div value of 0x1 results in a pre-divider of
304 pre-div = <0x3>;
305 podf = <0x0F>;
306 pinmuxes = <&iomuxcgpr 0x4 0x80000>;
307 interrupts = <56 0>;
308 dmas = <&edma0 0 19>, <&edma0 0 20>;
311 * cannot be 0
314 nxp,tx-dma-channel = <0>;
322 #size-cells = <0>;
324 reg = <0x401e8000 0x4000>;
325 clocks = <&ccm IMX_CCM_SAI3_CLK 0x7C 22>;
328 pre-div = <0>;
330 pll-clocks = <&anatop 0x70 0xC000 0>,
331 <&anatop 0x70 0x7F 32>,
332 <&anatop 0x70 0x180000 1>,
333 <&anatop 0x80 0x3FFFFFFF 77>,
334 <&anatop 0x90 0x3FFFFFFF 100>;
336 pinmuxes = <&iomuxcgpr 0x4 0x200000>;
337 interrupts = <58 0>, <59 0>;
338 dmas = <&edma0 0 83>, <&edma0 0 84>;
340 nxp,tx-channel = <0>;
393 interrupts = <24 0>;