Lines Matching +full:reg +full:- +full:io +full:- +full:width
1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
5 #include <zephyr/dt-bindings/adc/nrf-saadc-v3.h>
6 #include <zephyr/dt-bindings/regulator/nrf5x.h>
10 zephyr,bt-hci = &bt_hci_controller;
12 zephyr,flash-controller = &flash_controller;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m4f";
22 reg = <0>;
23 #address-cells = <1>;
24 #size-cells = <1>;
27 compatible = "arm,armv7m-itm";
28 reg = <0xe0000000 0x1000>;
29 swo-ref-frequency = <32000000>;
36 compatible = "nordic,nrf-ficr";
37 reg = <0x10000000 0x1000>;
38 #nordic,ficr-cells = <1>;
43 compatible = "nordic,nrf-uicr";
44 reg = <0x10001000 0x1000>;
49 compatible = "mmio-sram";
53 compatible = "nordic,nrf-clock";
54 reg = <0x40000000 0x1000>;
60 compatible = "nordic,nrf-power";
61 reg = <0x40000000 0x1000>;
64 #address-cells = <1>;
65 #size-cells = <1>;
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "nordic,nrf-gpregret";
71 reg = <0x4000051c 0x1>;
76 #address-cells = <1>;
77 #size-cells = <1>;
78 compatible = "nordic,nrf-gpregret";
79 reg = <0x40000520 0x1>;
84 compatible = "nordic,nrf5x-regulator";
85 reg = <0x40000578 0x1>;
86 regulator-name = "REG1";
87 regulator-initial-mode = <NRF5X_REG_MODE_LDO>;
92 compatible = "nordic,nrf-radio";
93 reg = <0x40001000 0x1000>;
96 ieee802154-supported;
97 ble-2mbps-supported;
98 ble-coded-phy-supported;
99 tx-high-power-supported;
102 compatible = "nordic,nrf-ieee802154";
110 compatible = "zephyr,bt-hci-ll-sw-split";
117 /* compatible = "nordic,nrf-uarte" or "nordic,nrf-uart"; */
118 compatible = "nordic,nrf-uarte";
119 reg = <0x40002000 0x1000>;
128 * compatible = "nordic,nrf-twi" or
129 * "nordic,nrf-twim" or
130 * "nordic,nrf-twis".
132 compatible = "nordic,nrf-twim";
133 #address-cells = <1>;
134 #size-cells = <0>;
135 reg = <0x40003000 0x1000>;
137 easydma-maxcnt-bits = <16>;
139 zephyr,pm-device-runtime-auto;
146 * compatible = "nordic,nrf-spi" or
147 * "nordic,nrf-spim" or
148 * "nordic,nrf-spis".
150 compatible = "nordic,nrf-spim";
151 #address-cells = <1>;
152 #size-cells = <0>;
153 reg = <0x40003000 0x1000>;
155 max-frequency = <DT_FREQ_M(8)>;
156 easydma-maxcnt-bits = <16>;
164 * compatible = "nordic,nrf-twi" or
165 * "nordic,nrf-twim" or
166 * "nordic,nrf-twis".
168 compatible = "nordic,nrf-twim";
169 #address-cells = <1>;
170 #size-cells = <0>;
171 reg = <0x40004000 0x1000>;
173 easydma-maxcnt-bits = <16>;
175 zephyr,pm-device-runtime-auto;
182 * compatible = "nordic,nrf-spi" or
183 * "nordic,nrf-spim" or
184 * "nordic,nrf-spis".
186 compatible = "nordic,nrf-spim";
187 #address-cells = <1>;
188 #size-cells = <0>;
189 reg = <0x40004000 0x1000>;
191 max-frequency = <DT_FREQ_M(8)>;
192 easydma-maxcnt-bits = <16>;
197 compatible = "nordic,nrf-nfct";
198 reg = <0x40005000 0x1000>;
204 compatible = "nordic,nrf-gpiote";
205 reg = <0x40006000 0x1000>;
212 compatible = "nordic,nrf-saadc";
213 reg = <0x40007000 0x1000>;
216 #io-channel-cells = <1>;
217 zephyr,pm-device-runtime-auto;
221 compatible = "nordic,nrf-timer";
223 reg = <0x40008000 0x1000>;
224 cc-num = <4>;
225 max-bit-width = <32>;
231 compatible = "nordic,nrf-timer";
233 reg = <0x40009000 0x1000>;
234 cc-num = <4>;
235 max-bit-width = <32>;
241 compatible = "nordic,nrf-timer";
243 reg = <0x4000a000 0x1000>;
244 cc-num = <4>;
245 max-bit-width = <32>;
251 compatible = "nordic,nrf-rtc";
252 reg = <0x4000b000 0x1000>;
253 cc-num = <3>;
256 clock-frequency = <32768>;
261 compatible = "nordic,nrf-temp";
262 reg = <0x4000c000 0x1000>;
268 compatible = "nordic,nrf-rng";
269 reg = <0x4000d000 0x1000>;
275 compatible = "nordic,nrf-ecb";
276 reg = <0x4000e000 0x1000>;
282 compatible = "nordic,nrf-ccm";
283 reg = <0x4000f000 0x1000>;
285 length-field-length-8-bits;
290 compatible = "nordic,nrf-wdt";
291 reg = <0x40010000 0x1000>;
297 compatible = "nordic,nrf-rtc";
298 reg = <0x40011000 0x1000>;
299 cc-num = <4>;
302 clock-frequency = <32768>;
307 compatible = "nordic,nrf-qdec";
308 reg = <0x40012000 0x1000>;
315 * Use compatible "nordic,nrf-comp" to configure as COMP
316 * Use compatible "nordic,nrf-lpcomp" to configure as LPCOMP
318 compatible = "nordic,nrf-comp";
319 reg = <0x40013000 0x1000>;
325 compatible = "nordic,nrf-egu", "nordic,nrf-swi";
326 reg = <0x40014000 0x1000>;
332 compatible = "nordic,nrf-egu", "nordic,nrf-swi";
333 reg = <0x40015000 0x1000>;
339 compatible = "nordic,nrf-egu", "nordic,nrf-swi";
340 reg = <0x40016000 0x1000>;
346 compatible = "nordic,nrf-egu", "nordic,nrf-swi";
347 reg = <0x40017000 0x1000>;
353 compatible = "nordic,nrf-egu", "nordic,nrf-swi";
354 reg = <0x40018000 0x1000>;
360 compatible = "nordic,nrf-egu", "nordic,nrf-swi";
361 reg = <0x40019000 0x1000>;
367 compatible = "nordic,nrf-timer";
369 reg = <0x4001a000 0x1000>;
370 cc-num = <6>;
371 max-bit-width = <32>;
377 compatible = "nordic,nrf-timer";
379 reg = <0x4001b000 0x1000>;
380 cc-num = <6>;
381 max-bit-width = <32>;
387 compatible = "nordic,nrf-pwm";
388 reg = <0x4001c000 0x1000>;
391 #pwm-cells = <3>;
395 compatible = "nordic,nrf-pdm";
396 reg = <0x4001d000 0x1000>;
402 compatible = "nordic,nrf-acl";
403 reg = <0x4001e000 0x1000>;
407 flash_controller: flash-controller@4001e000 {
408 compatible = "nordic,nrf52-flash-controller";
409 reg = <0x4001e000 0x1000>;
410 partial-erase;
412 #address-cells = <1>;
413 #size-cells = <1>;
417 compatible = "soc-nv-flash";
418 erase-block-size = <4096>;
419 write-block-size = <4>;
424 compatible = "nordic,nrf-ppi";
425 reg = <0x4001f000 0x1000>;
430 compatible = "nordic,nrf-mwu";
431 reg = <0x40020000 0x1000>;
436 compatible = "nordic,nrf-pwm";
437 reg = <0x40021000 0x1000>;
440 #pwm-cells = <3>;
444 compatible = "nordic,nrf-pwm";
445 reg = <0x40022000 0x1000>;
448 #pwm-cells = <3>;
455 * compatible = "nordic,nrf-spi" or
456 * "nordic,nrf-spim" or
457 * "nordic,nrf-spis".
459 compatible = "nordic,nrf-spim";
460 #address-cells = <1>;
461 #size-cells = <0>;
462 reg = <0x40023000 0x1000>;
464 max-frequency = <DT_FREQ_M(8)>;
465 easydma-maxcnt-bits = <16>;
470 compatible = "nordic,nrf-rtc";
471 reg = <0x40024000 0x1000>;
472 cc-num = <4>;
475 clock-frequency = <32768>;
480 compatible = "nordic,nrf-i2s";
481 #address-cells = <1>;
482 #size-cells = <0>;
483 reg = <0x40025000 0x1000>;
489 compatible = "nordic,nrf-usbd";
490 reg = <0x40027000 0x1000>;
492 num-bidir-endpoints = <1>;
493 num-in-endpoints = <7>;
494 num-out-endpoints = <7>;
495 num-isoin-endpoints = <1>;
496 num-isoout-endpoints = <1>;
501 compatible = "nordic,nrf-uarte";
502 reg = <0x40028000 0x1000>;
508 compatible = "nordic,nrf-qspi";
509 #address-cells = <1>;
510 #size-cells = <0>;
511 reg = <0x40029000 0x1000>, <0x12000000 0x8000000>;
512 reg-names = "qspi", "qspi_mm";
518 compatible = "nordic,nrf-pwm";
519 reg = <0x4002d000 0x1000>;
522 #pwm-cells = <3>;
526 compatible = "nordic,nrf-spim";
527 #address-cells = <1>;
528 #size-cells = <0>;
529 reg = <0x4002f000 0x1000>;
531 max-frequency = <DT_FREQ_M(32)>;
532 easydma-maxcnt-bits = <16>;
533 rx-delay-supported;
534 rx-delay = <2>;
539 compatible = "nordic,nrf-gpio";
540 gpio-controller;
541 reg = <0x50000000 0x200
543 #gpio-cells = <2>;
546 gpiote-instance = <&gpiote>;
550 compatible = "nordic,nrf-gpio";
551 gpio-controller;
552 reg = <0x50000300 0x200
554 #gpio-cells = <2>;
558 gpiote-instance = <&gpiote>;
562 compatible = "nordic,cryptocell", "arm,cryptocell-310";
563 reg = <0x5002a000 0x1000>, <0x5002b000 0x1000>;
564 reg-names = "wrapper", "core";
572 arm,num-irq-priority-bits = <3>;