Lines Matching +full:pcr +full:- +full:cells
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m4";
23 cpu-power-states = <&idle &suspend_to_ram>;
26 power-states {
28 compatible = "zephyr,power-state";
29 power-state-name = "suspend-to-idle";
30 min-residency-us = <1000000>;
34 compatible = "zephyr,power-state";
35 power-state-name = "suspend-to-ram";
36 min-residency-us = <2000000>;
46 compatible = "mmio-sram";
51 i2c-smb-0 = &i2c_smb_0;
52 i2c-smb-1 = &i2c_smb_1;
53 i2c-smb-2 = &i2c_smb_2;
54 i2c-smb-3 = &i2c_smb_3;
55 i2c-smb-4 = &i2c_smb_4;
60 compatible = "microchip,xec-ecs";
63 pcr: pcr@40080100 { label
64 compatible = "microchip,xec-pcr";
66 reg-names = "pcrr", "vbatr";
67 core-clock-div = <1>;
69 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
70 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
71 clk32kmon-period-min = <1435>;
72 clk32kmon-period-max = <1495>;
73 clk32kmon-duty-cycle-var-max = <132>;
74 clk32kmon-valid-min = <4>;
75 xtal-enable-delay-ms = <300>;
76 pll-lock-timeout-ms = <30>;
77 #clock-cells = <3>;
81 #address-cells = <1>;
82 #size-cells = <1>;
87 girq-id = <15>;
92 pinctrl: pin-controller@40081000 {
93 compatible = "microchip,xec-pinctrl";
94 #address-cells = <1>;
95 #size-cells = <1>;
99 compatible = "microchip,xec-gpio";
103 gpio-controller;
104 port-id = <0>;
105 girq-id = <11>;
106 #gpio-cells=<2>;
109 compatible = "microchip,xec-gpio";
113 gpio-controller;
114 port-id = <1>;
115 girq-id = <10>;
116 #gpio-cells=<2>;
119 compatible = "microchip,xec-gpio";
122 gpio-controller;
124 port-id = <2>;
125 girq-id = <9>;
126 #gpio-cells=<2>;
129 compatible = "microchip,xec-gpio";
132 gpio-controller;
134 port-id = <3>;
135 girq-id = <8>;
136 #gpio-cells=<2>;
139 compatible = "microchip,xec-gpio";
142 gpio-controller;
144 port-id = <4>;
145 girq-id = <12>;
146 #gpio-cells=<2>;
149 compatible = "microchip,xec-gpio";
152 gpio-controller;
154 port-id = <5>;
155 girq-id = <26>;
156 #gpio-cells=<2>;
160 compatible = "microchip,xec-rtos-timer";
165 bbram: bb-ram@4000a800 {
166 compatible = "microchip,xec-bbram";
168 reg-names = "memory";
171 compatible = "microchip,xec-watchdog";
178 compatible = "microchip,xec-uart";
181 clock-frequency = <1843200>;
182 current-speed = <38400>;
189 compatible = "microchip,xec-uart";
192 clock-frequency = <1843200>;
193 current-speed = <38400>;
200 compatible = "microchip,xec-uart";
203 clock-frequency = <1843200>;
204 current-speed = <38400>;
212 compatible = "microchip,xec-i2c";
214 clock-frequency = <I2C_BITRATE_STANDARD>;
217 #address-cells = <1>;
218 #size-cells = <0>;
221 girq-bit = <0>;
225 compatible = "microchip,xec-i2c";
227 clock-frequency = <I2C_BITRATE_STANDARD>;
230 #address-cells = <1>;
231 #size-cells = <0>;
234 girq-bit = <1>;
238 compatible = "microchip,xec-i2c";
240 clock-frequency = <I2C_BITRATE_STANDARD>;
243 #address-cells = <1>;
244 #size-cells = <0>;
247 girq-bit = <2>;
251 compatible = "microchip,xec-i2c";
253 clock-frequency = <I2C_BITRATE_STANDARD>;
256 #address-cells = <1>;
257 #size-cells = <0>;
260 girq-bit = <3>;
264 compatible = "microchip,xec-i2c";
266 clock-frequency = <I2C_BITRATE_STANDARD>;
269 #address-cells = <1>;
270 #size-cells = <0>;
273 girq-bit = <4>;
277 compatible = "microchip,xec-espi";
280 #address-cells = <1>;
281 #size-cells = <0>;
285 compatible = "microchip,xec-espi-saf";
289 #address-cells = <1>;
290 #size-cells = <0>;
295 compatible = "microchip,xec-timer";
296 clock-frequency = <48000000>;
299 max-value = <0xFFFF>;
306 compatible = "microchip,xec-timer";
307 clock-frequency = <48000000>;
310 max-value = <0xFFFF>;
323 compatible = "microchip,xec-timer";
324 clock-frequency = <48000000>;
327 max-value = <0xFFFFFFFF>;
334 compatible = "microchip,xec-timer";
335 clock-frequency = <48000000>;
338 max-value = <0xFFFFFFFF>;
354 compatible = "microchip,xec-ps2";
359 #address-cells = <1>;
360 #size-cells = <0>;
364 compatible = "microchip,xec-ps2";
369 #address-cells = <1>;
370 #size-cells = <0>;
374 compatible = "microchip,xec-pwm";
378 #pwm-cells = <3>;
381 compatible = "microchip,xec-pwm";
385 #pwm-cells = <3>;
388 compatible = "microchip,xec-pwm";
392 #pwm-cells = <3>;
395 compatible = "microchip,xec-pwm";
399 #pwm-cells = <3>;
402 compatible = "microchip,xec-pwm";
406 #pwm-cells = <3>;
409 compatible = "microchip,xec-pwm";
413 #pwm-cells = <3>;
416 compatible = "microchip,xec-pwm";
420 #pwm-cells = <3>;
423 compatible = "microchip,xec-pwm";
427 #pwm-cells = <3>;
430 compatible = "microchip,xec-pwm";
434 #pwm-cells = <3>;
437 compatible = "microchip,xec-adc";
443 #io-channel-cells = <1>;
448 compatible = "microchip,xec-kbd";
454 #address-cells = <1>;
455 #size-cells = <0>;
458 compatible = "microchip,xec-peci";
463 #address-cells = <1>;
464 #size-cells = <0>;
467 compatible = "microchip,xec-qmspi";
470 clock-frequency = <12000000>;
479 #address-cells = <1>;
480 #size-cells = <0>;
484 compatible = "microchip,xec-tach";
490 #address-cells = <1>;
491 #size-cells = <0>;
494 compatible = "microchip,xec-tach";
500 #address-cells = <1>;
501 #size-cells = <0>;
504 compatible = "microchip,xec-tach";
510 #address-cells = <1>;
511 #size-cells = <0>;
514 compatible = "microchip,xec-tach";
520 #address-cells = <1>;
521 #size-cells = <0>;
548 arm,num-irq-priority-bits = <3>;