Lines Matching +full:0 +full:x80
13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
39 reg = <0x20000000 DT_SIZE_K(244)>;
45 reg = <0x2003D000 DT_SIZE_K(12)>;
51 reg = <0x40400000 0x20000>;
56 reg = <0x40400000 0x4000>;
63 reg = <0x40410000 0x80>;
64 interrupts = <0 4>;
72 reg = <0x40410080 0x80>;
81 reg = <0x40410100 0x80>;
90 reg = <0x40410180 0x80>;
99 reg = <0x40410200 0x80>;
108 reg = <0x40410280 0x80>;
118 reg = <0x401d0000 0x10000>;
125 reg = <0x40590000 0xfd0>;
131 reg = <0x405a0000 0xfd0>;
137 reg = <0x405b0000 0xfd0>;
144 reg = <0x4020c000 0x10>;
151 reg = <0x4020d000 0x40>;
158 reg = <0x40220000 0x10000>;
166 reg = <0x404a0000 0x80>;
173 reg = <0x404a0080 0x80>;
180 reg = <0x404a8000 0x80>;
187 reg = <0x404a8080 0x80>;
194 reg = <0x404a8100 0x80>;
201 reg = <0x404a8180 0x80>;
208 reg = <0x404a8200 0x80>;
215 reg = <0x404a8280 0x80>;
222 reg = <0x404a8300 0x80>;
230 reg = <0x404a0000 0x80>;
238 reg = <0x404a0080 0x80>;
246 reg = <0x404a8000 0x80>;
254 reg = <0x404a8080 0x80>;
262 reg = <0x404a8100 0x80>;
270 reg = <0x404a8180 0x80>;
278 reg = <0x404a8200 0x80>;
286 reg = <0x404a8280 0x80>;
294 reg = <0x404a8300 0x80>;
304 reg = <0x40180000 0x10000>;
326 reg = <0x42000000 0x6186A0>;