Lines Matching full:rctl
51 rctl: reset-controller { label
52 compatible = "gd,gd32-rctl";
78 resets = <&rctl GD32_RESET_USART0>;
87 resets = <&rctl GD32_RESET_USART1>;
96 resets = <&rctl GD32_RESET_USART2>;
105 resets = <&rctl GD32_RESET_UART3>;
114 resets = <&rctl GD32_RESET_UART4>;
123 resets = <&rctl GD32_RESET_SPI0>;
134 resets = <&rctl GD32_RESET_SPI1>;
145 resets = <&rctl GD32_RESET_SPI2>;
156 resets = <&rctl GD32_RESET_ADC0>;
167 resets = <&rctl GD32_RESET_ADC1>;
178 resets = <&rctl GD32_RESET_ADC2>;
215 resets = <&rctl GD32_RESET_WWDGT>;
233 resets = <&rctl GD32_RESET_GPIOA>;
243 resets = <&rctl GD32_RESET_GPIOB>;
253 resets = <&rctl GD32_RESET_GPIOC>;
263 resets = <&rctl GD32_RESET_GPIOD>;
273 resets = <&rctl GD32_RESET_GPIOE>;
283 resets = <&rctl GD32_RESET_GPIOF>;
293 resets = <&rctl GD32_RESET_GPIOG>;
304 resets = <&rctl GD32_RESET_TIMER0>;
322 resets = <&rctl GD32_RESET_TIMER2>;
339 resets = <&rctl GD32_RESET_TIMER3>;
356 resets = <&rctl GD32_RESET_TIMER5>;
367 resets = <&rctl GD32_RESET_TIMER6>;
378 resets = <&rctl GD32_RESET_TIMER7>;
396 resets = <&rctl GD32_RESET_TIMER8>;
413 resets = <&rctl GD32_RESET_TIMER9>;
430 resets = <&rctl GD32_RESET_TIMER10>;
447 resets = <&rctl GD32_RESET_TIMER11>;
464 resets = <&rctl GD32_RESET_TIMER12>;
481 resets = <&rctl GD32_RESET_TIMER13>;