Lines Matching +full:max +full:- +full:erase +full:- +full:time +full:- +full:ms
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/adc/gd32f3x0.h>
12 #include <zephyr/dt-bindings/clock/gd32f3x0-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32f3x0.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 clock-frequency = <DT_FREQ_M(108)>;
22 compatible = "arm,cortex-m4f";
29 compatible = "mmio-sram";
32 rcu: reset-clock-controller@40021000 {
33 compatible = "gd,gd32-rcu";
37 cctl: clock-controller {
38 compatible = "gd,gd32-cctl";
39 #clock-cells = <1>;
43 rctl: reset-controller {
44 compatible = "gd,gd32-rctl";
45 #reset-cells = <1>;
50 fmc: flash-controller@40022000 {
51 compatible = "gd,gd32-flash-controller";
54 #address-cells = <1>;
55 #size-cells = <1>;
58 compatible = "gd,gd32-nv-flash-v1", "soc-nv-flash";
59 write-block-size = <2>;
60 max-erase-time-ms = <300>;
61 page-size = <DT_SIZE_K(1)>;
66 compatible = "gd,gd32-usart";
75 compatible = "gd,gd32-usart";
84 compatible = "gd,gd32-adc";
87 rcu-clock-source = <GD32_RCU_ADCCK_APB2_DIV4>;
92 #io-channel-cells = <1>;
96 compatible = "gd,gd32-dma";
100 dma-channels = <7>;
101 #dma-cells = <2>;
106 compatible = "gd,gd32-fwdgt";
112 compatible = "gd,gd32-wwdgt";
120 pinctrl: pin-controller@48000000 {
121 compatible = "gd,gd32-pinctrl-af";
123 #address-cells = <1>;
124 #size-cells = <1>;
128 compatible = "gd,gd32-gpio";
129 gpio-controller;
130 #gpio-cells = <2>;
138 compatible = "gd,gd32-gpio";
139 gpio-controller;
140 #gpio-cells = <2>;
148 compatible = "gd,gd32-gpio";
149 gpio-controller;
150 #gpio-cells = <2>;
158 compatible = "gd,gd32-gpio";
159 gpio-controller;
160 #gpio-cells = <2>;
168 compatible = "gd,gd32-gpio";
169 gpio-controller;
170 #gpio-cells = <2>;
181 arm,num-irq-priority-bits = <4>;