Lines Matching full:resets
71 resets = <&rctl GD32_RESET_USART0>;
80 resets = <&rctl GD32_RESET_USART1>;
89 resets = <&rctl GD32_RESET_USART2>;
98 resets = <&rctl GD32_RESET_UART3>;
107 resets = <&rctl GD32_RESET_UART4>;
115 resets = <&rctl GD32_RESET_DAC>;
130 resets = <&rctl GD32_RESET_I2C0>;
143 resets = <&rctl GD32_RESET_I2C1>;
177 resets = <&rctl GD32_RESET_WWDGT>;
195 resets = <&rctl GD32_RESET_GPIOA>;
205 resets = <&rctl GD32_RESET_GPIOB>;
215 resets = <&rctl GD32_RESET_GPIOC>;
225 resets = <&rctl GD32_RESET_GPIOD>;
235 resets = <&rctl GD32_RESET_GPIOE>;
246 resets = <&rctl GD32_RESET_TIMER0>;
264 resets = <&rctl GD32_RESET_TIMER1>;
281 resets = <&rctl GD32_RESET_TIMER2>;
298 resets = <&rctl GD32_RESET_TIMER3>;
315 resets = <&rctl GD32_RESET_TIMER4>;
332 resets = <&rctl GD32_RESET_TIMER5>;
343 resets = <&rctl GD32_RESET_TIMER6>;
354 resets = <&rctl GD32_RESET_TIMER7>;
372 resets = <&rctl GD32_RESET_TIMER8>;
389 resets = <&rctl GD32_RESET_TIMER9>;
406 resets = <&rctl GD32_RESET_TIMER10>;
423 resets = <&rctl GD32_RESET_TIMER11>;
440 resets = <&rctl GD32_RESET_TIMER12>;
457 resets = <&rctl GD32_RESET_TIMER13>;