Lines Matching +full:cc +full:- +full:num
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/gd32a50x-clocks.h>
14 #include <zephyr/dt-bindings/reset/gd32a50x.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-m33f";
24 #address-cells = <1>;
25 #size-cells = <1>;
26 clock-frequency = <DT_FREQ_M(100)>;
29 compatible = "arm,armv8m-mpu";
37 compatible = "mmio-sram";
40 rcu: reset-clock-controller@40021000 {
41 compatible = "gd,gd32-rcu";
45 cctl: clock-controller {
46 compatible = "gd,gd32-cctl";
47 #clock-cells = <1>;
51 rctl: reset-controller {
52 compatible = "gd,gd32-rctl";
53 #reset-cells = <1>;
58 fmc: flash-controller@40022000 {
59 compatible = "gd,gd32-flash-controller";
62 #address-cells = <1>;
63 #size-cells = <1>;
66 compatible = "gd,gd32-nv-flash-v2", "soc-nv-flash";
67 write-block-size = <4>;
68 max-erase-time-ms = <2578>;
69 bank0-page-size = <DT_SIZE_K(1)>;
70 bank1-page-size = <DT_SIZE_K(1)>;
75 compatible = "gd,gd32-usart";
84 compatible = "gd,gd32-usart";
93 compatible = "gd,gd32-usart";
102 compatible = "gd,gd32-dac";
106 num-channels = <1>;
108 #io-channel-cells = <1>;
112 compatible = "gd,gd32-i2c";
114 #address-cells = <1>;
115 #size-cells = <0>;
116 clock-frequency = <I2C_BITRATE_STANDARD>;
118 interrupt-names = "event", "error";
125 compatible = "gd,gd32-i2c";
127 #address-cells = <1>;
128 #size-cells = <0>;
129 clock-frequency = <I2C_BITRATE_STANDARD>;
131 interrupt-names = "event", "error";
138 compatible = "gd,gd32-spi";
144 #address-cells = <1>;
145 #size-cells = <0>;
149 compatible = "gd,gd32-spi";
155 #address-cells = <1>;
156 #size-cells = <0>;
160 compatible = "gd,gd32-adc";
167 #io-channel-cells = <1>;
171 compatible = "gd,gd32-adc";
178 #io-channel-cells = <1>;
182 compatible = "gd,gd32-syscfg";
187 exti: interrupt-controller@40010400 {
188 compatible = "gd,gd32-exti";
189 interrupt-controller;
190 #interrupt-cells = <1>;
192 num-lines = <25>;
195 interrupt-names = "line0", "line1", "line2", "line3",
196 "line4", "line5-9", "line10-15";
201 compatible = "gd,gd32-fwdgt";
207 compatible = "gd,gd32-wwdgt";
215 pinctrl: pin-controller@48000000 {
216 compatible = "gd,gd32-pinctrl-af";
218 #address-cells = <1>;
219 #size-cells = <1>;
223 compatible = "gd,gd32-gpio";
224 gpio-controller;
225 #gpio-cells = <2>;
233 compatible = "gd,gd32-gpio";
234 gpio-controller;
235 #gpio-cells = <2>;
243 compatible = "gd,gd32-gpio";
244 gpio-controller;
245 #gpio-cells = <2>;
253 compatible = "gd,gd32-gpio";
254 gpio-controller;
255 #gpio-cells = <2>;
263 compatible = "gd,gd32-gpio";
264 gpio-controller;
265 #gpio-cells = <2>;
273 compatible = "gd,gd32-gpio";
274 gpio-controller;
275 #gpio-cells = <2>;
284 compatible = "gd,gd32-timer";
287 interrupt-names = "brk", "up", "trgcom", "cc";
290 is-advanced;
295 compatible = "gd,gd32-pwm";
297 #pwm-cells = <3>;
302 compatible = "gd,gd32-timer";
305 interrupt-names = "global";
308 is-32bit;
313 compatible = "gd,gd32-pwm";
315 #pwm-cells = <3>;
320 compatible = "gd,gd32-timer";
323 interrupt-names = "global";
331 compatible = "gd,gd32-timer";
334 interrupt-names = "global";
342 compatible = "gd,gd32-timer";
345 interrupt-names = "brk", "up", "trgcom", "cc";
348 is-advanced;
353 compatible = "gd,gd32-pwm";
355 #pwm-cells = <3>;
360 compatible = "gd,gd32-timer";
363 interrupt-names = "global";
370 compatible = "gd,gd32-pwm";
372 #pwm-cells = <3>;
377 compatible = "gd,gd32-timer";
380 interrupt-names = "global";
387 compatible = "gd,gd32-pwm";
389 #pwm-cells = <3>;
394 compatible = "gd,gd32-dma";
399 dma-channels = <7>;
401 #dma-cells = <2>;
406 compatible = "gd,gd32-dma";
411 dma-channels = <5>;
413 #dma-cells = <2>;
420 arm,num-irq-priority-bits = <4>;