Lines Matching +full:num +full:- +full:tc
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
15 adc-0 = &adc0;
16 adc-1 = &adc1;
18 port-a = &porta;
19 port-b = &portb;
20 port-c = &portc;
21 port-d = &portd;
23 sercom-0 = &sercom0;
24 sercom-1 = &sercom1;
25 sercom-2 = &sercom2;
26 sercom-3 = &sercom3;
27 sercom-4 = &sercom4;
28 sercom-5 = &sercom5;
29 sercom-6 = &sercom6;
30 sercom-7 = &sercom7;
32 tc-0 = &tc0;
33 tc-2 = &tc2;
34 tc-4 = &tc4;
35 tc-6 = &tc6;
37 tcc-0 = &tcc0;
38 tcc-1 = &tcc1;
39 tcc-2 = &tcc2;
40 tcc-3 = &tcc3;
41 tcc-4 = &tcc4;
48 zephyr,flash-controller = &nvmctrl;
52 #address-cells = <1>;
53 #size-cells = <0>;
56 compatible = "arm,cortex-m4f";
59 #address-cells = <1>;
60 #size-cells = <1>;
65 compatible = "arm,armv7m-mpu";
73 compatible = "mmio-sram";
78 compatible = "mmio-sram";
83 compatible = "atmel,sam0-id";
91 compatible = "atmel,samd5x-mclk";
94 #clock-cells = <2>;
98 compatible = "atmel,samd5x-gclk";
101 #clock-cells = <1>;
105 compatible = "atmel,sam0-nvmctrl";
109 #address-cells = <1>;
110 #size-cells = <1>;
112 lock-regions = <32>;
115 compatible = "soc-nv-flash";
117 write-block-size = <8>;
122 compatible = "atmel,sam0-dmac";
127 #dma-cells = <2>;
131 compatible = "atmel,sam0-eic";
140 compatible = "atmel,sam0-pinmux";
145 compatible = "atmel,sam0-pinmux";
150 compatible = "atmel,sam0-pinmux";
155 compatible = "atmel,sam0-pinmux";
160 compatible = "atmel,sam0-watchdog";
166 compatible = "atmel,sam0-sercom";
170 clock-names = "GCLK", "MCLK";
175 compatible = "atmel,sam0-sercom";
179 clock-names = "GCLK", "MCLK";
184 compatible = "atmel,sam0-sercom";
188 clock-names = "GCLK", "MCLK";
193 compatible = "atmel,sam0-sercom";
197 clock-names = "GCLK", "MCLK";
202 compatible = "atmel,sam0-sercom";
206 clock-names = "GCLK", "MCLK";
211 compatible = "atmel,sam0-sercom";
215 clock-names = "GCLK", "MCLK";
220 compatible = "atmel,sam0-sercom";
224 clock-names = "GCLK", "MCLK";
229 compatible = "atmel,sam0-sercom";
233 clock-names = "GCLK", "MCLK";
238 compatible = "atmel,sam0-pinctrl";
241 #address-cells = <1>;
242 #size-cells = <1>;
245 compatible = "atmel,sam0-gpio";
248 #atmel,pin-cells = <2>;
249 #gpio-cells = <2>;
251 gpio-controller;
255 compatible = "atmel,sam0-gpio";
258 #atmel,pin-cells = <2>;
259 #gpio-cells = <2>;
261 gpio-controller;
265 compatible = "atmel,sam0-gpio";
268 #atmel,pin-cells = <2>;
269 #gpio-cells = <2>;
271 gpio-controller;
275 compatible = "atmel,sam0-gpio";
278 #atmel,pin-cells = <2>;
279 #gpio-cells = <2>;
281 gpio-controller;
286 compatible = "atmel,sam0-usb";
291 num-bidir-endpoints = <8>;
295 compatible = "atmel,sam-trng";
301 compatible = "atmel,sam0-rtc";
306 clock-generator = <0>;
310 compatible = "atmel,sam0-adc";
313 interrupt-names = "overrun", "resrdy";
315 clock-names = "GCLK", "MCLK";
318 #io-channel-cells = <1>;
322 * - table 54-8, section 54.6, page 2020
323 * - table 54-24, section 54.10.4, page 2031
324 * -> 48 MHz GCLK(2) / 4 = 12 MHz
328 calib-offset = <0>;
332 compatible = "atmel,sam0-adc";
335 interrupt-names = "overrun", "resrdy";
337 clock-names = "GCLK", "MCLK";
340 #io-channel-cells = <1>;
344 * - table 54-8, section 54.6, page 2020
345 * - table 54-24, section 54.10.4, page 2031
346 * -> 48 MHz GCLK(2) / 4 = 12 MHz
350 calib-offset = <14>;
353 tc0: tc@40003800 {
354 compatible = "atmel,sam0-tc32";
358 clock-names = "GCLK", "MCLK";
362 tc2: tc@4101a000 {
363 compatible = "atmel,sam0-tc32";
367 clock-names = "GCLK", "MCLK";
371 tc4: tc@42001400 {
372 compatible = "atmel,sam0-tc32";
376 clock-names = "GCLK", "MCLK";
380 tc6: tc@43001400 {
381 compatible = "atmel,sam0-tc32";
385 clock-names = "GCLK", "MCLK";
390 compatible = "atmel,sam0-tcc";
395 clock-names = "GCLK", "MCLK";
399 counter-size = <24>;
403 compatible = "atmel,sam0-tcc";
407 clock-names = "GCLK", "MCLK";
411 counter-size = <24>;
415 compatible = "atmel,sam0-tcc";
419 clock-names = "GCLK", "MCLK";
423 counter-size = <16>;
427 compatible = "atmel,sam0-tcc";
431 clock-names = "GCLK", "MCLK";
435 counter-size = <16>;
439 compatible = "atmel,sam0-tcc";
443 clock-names = "GCLK", "MCLK";
447 counter-size = <16>;
453 arm,num-irq-priority-bits = <3>;