Lines Matching +full:min +full:- +full:residency +full:- +full:us
1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
6 #include <zephyr/dt-bindings/adc/adc.h>
7 #include <zephyr/dt-bindings/i2c/i2c.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 uartclk: apb-pclk {
13 compatible = "fixed-clock";
14 clock-frequency = <DT_FREQ_M(24)>;
15 #clock-cells = <0>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,cortex-m4f";
26 cpu-power-states = <&idle &suspend_to_ram>;
27 #address-cells = <1>;
28 #size-cells = <1>;
31 compatible = "arm,armv7m-itm";
33 swo-ref-frequency = <DT_FREQ_M(48)>;
36 power-states {
38 compatible = "zephyr,power-state";
39 power-state-name = "suspend-to-idle";
42 * transition time are both lower than 1us, but
46 min-residency-us = <100>;
47 exit-latency-us = <5>;
51 compatible = "zephyr,power-state";
52 power-state-name = "suspend-to-ram";
55 * time is lower than 1us and deepsleep_to_run
56 * transition time is about 25us, but considering
59 min-residency-us = <2000>;
60 exit-latency-us = <125>;
67 compatible = "zephyr,memory-region";
69 zephyr,memory-region = "ITCM";
74 compatible = "mmio-sram";
79 compatible = "ambiq,apollo4p", "ambiq,apollo4x", "simple-bus";
81 flash: flash-controller@18000 {
82 compatible = "ambiq,flash-controller";
85 #address-cells = <1>;
86 #size-cells = <1>;
90 compatible = "soc-nv-flash";
98 #pwrcfg-cells = <2>;
112 clock-frequency = <DT_FREQ_M(6)>;
113 clk-source = <1>;
121 interrupt-names = "UART0";
130 interrupt-names = "UART1";
140 interrupt-names = "UART2";
150 interrupt-names = "UART3";
159 #address-cells = <1>;
160 #size-cells = <0>;
169 #address-cells = <1>;
170 #size-cells = <0>;
179 #address-cells = <1>;
180 #size-cells = <0>;
189 #address-cells = <1>;
190 #size-cells = <0>;
199 #address-cells = <1>;
200 #size-cells = <0>;
209 #address-cells = <1>;
210 #size-cells = <0>;
219 #address-cells = <1>;
220 #size-cells = <0>;
229 #address-cells = <1>;
230 #size-cells = <0>;
239 #address-cells = <1>;
240 #size-cells = <0>;
249 #address-cells = <1>;
250 #size-cells = <0>;
259 #address-cells = <1>;
260 #size-cells = <0>;
269 #address-cells = <1>;
270 #size-cells = <0>;
279 #address-cells = <1>;
280 #size-cells = <0>;
289 #address-cells = <1>;
290 #size-cells = <0>;
299 #address-cells = <1>;
300 #size-cells = <0>;
309 #address-cells = <1>;
310 #size-cells = <0>;
320 interrupt-names = "ADC";
321 channel-count = <10>;
322 internal-vref-mv = <1190>;
324 #io-channel-cells = <1>;
332 #address-cells = <1>;
333 #size-cells = <0>;
342 #address-cells = <1>;
343 #size-cells = <0>;
352 #address-cells = <1>;
353 #size-cells = <0>;
362 alarms-count = <1>;
370 num-bidir-endpoints = <6>;
371 maximum-speed = "full-speed";
376 pinctrl: pin-controller@40010000 {
377 compatible = "ambiq,apollo4-pinctrl";
379 #address-cells = <1>;
380 #size-cells = <0>;
384 gpio-map-mask = <0xffffffe0 0xffffffc0>;
385 gpio-map-pass-thru = <0x1f 0x3f>;
386 gpio-map = <
393 #gpio-cells = <2>;
394 #address-cells = <1>;
395 #size-cells = <0>;
399 compatible = "ambiq,gpio-bank";
400 gpio-controller;
401 #gpio-cells = <2>;
408 compatible = "ambiq,gpio-bank";
409 gpio-controller;
410 #gpio-cells = <2>;
417 compatible = "ambiq,gpio-bank";
418 gpio-controller;
419 #gpio-cells = <2>;
426 compatible = "ambiq,gpio-bank";
427 gpio-controller;
428 #gpio-cells = <2>;
440 clock-frequency = <16>;
447 arm,num-irq-priority-bits = <3>;