Lines Matching +full:address +full:- +full:1
1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
6 #include <zephyr/dt-bindings/adc/adc.h>
7 #include <zephyr/dt-bindings/i2c/i2c.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 uartclk: apb-pclk {
13 compatible = "fixed-clock";
14 clock-frequency = <DT_FREQ_M(24)>;
15 #clock-cells = <0>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,cortex-m4f";
26 cpu-power-states = <&idle &suspend_to_ram>;
27 #address-cells = <1>;
28 #size-cells = <1>;
31 compatible = "arm,armv7m-itm";
33 swo-ref-frequency = <DT_FREQ_M(48)>;
36 power-states {
38 compatible = "zephyr,power-state";
39 power-state-name = "suspend-to-idle";
42 * transition time are both lower than 1us, but
46 min-residency-us = <100>;
47 exit-latency-us = <5>;
51 compatible = "zephyr,power-state";
52 power-state-name = "suspend-to-ram";
55 * time is lower than 1us and deepsleep_to_run
59 min-residency-us = <2000>;
60 exit-latency-us = <125>;
67 compatible = "zephyr,memory-region";
69 zephyr,memory-region = "ITCM";
74 compatible = "mmio-sram";
79 compatible = "ambiq,apollo4p", "ambiq,apollo4x", "simple-bus";
81 flash: flash-controller@18000 {
82 compatible = "ambiq,flash-controller";
85 #address-cells = <1>;
86 #size-cells = <1>;
90 compatible = "soc-nv-flash";
98 #pwrcfg-cells = <2>;
112 clock-frequency = <DT_FREQ_M(6)>;
113 clk-source = <1>;
121 interrupt-names = "UART0";
130 interrupt-names = "UART1";
140 interrupt-names = "UART2";
150 interrupt-names = "UART3";
158 #address-cells = <1>;
159 #size-cells = <0>;
167 #address-cells = <1>;
168 #size-cells = <0>;
176 #address-cells = <1>;
177 #size-cells = <0>;
185 #address-cells = <1>;
186 #size-cells = <0>;
194 #address-cells = <1>;
195 #size-cells = <0>;
203 #address-cells = <1>;
204 #size-cells = <0>;
212 #address-cells = <1>;
213 #size-cells = <0>;
221 #address-cells = <1>;
222 #size-cells = <0>;
230 #address-cells = <1>;
231 #size-cells = <0>;
239 #address-cells = <1>;
240 #size-cells = <0>;
248 #address-cells = <1>;
249 #size-cells = <0>;
257 #address-cells = <1>;
258 #size-cells = <0>;
266 #address-cells = <1>;
267 #size-cells = <0>;
275 #address-cells = <1>;
276 #size-cells = <0>;
284 #address-cells = <1>;
285 #size-cells = <0>;
293 #address-cells = <1>;
294 #size-cells = <0>;
303 interrupt-names = "ADC";
304 channel-count = <10>;
305 internal-vref-mv = <1190>;
307 #io-channel-cells = <1>;
315 #address-cells = <1>;
316 #size-cells = <0>;
325 #address-cells = <1>;
326 #size-cells = <0>;
335 #address-cells = <1>;
336 #size-cells = <0>;
345 alarms-count = <1>;
353 num-bidir-endpoints = <6>;
354 maximum-speed = "full-speed";
359 pinctrl: pin-controller@40010000 {
360 compatible = "ambiq,apollo4-pinctrl";
362 #address-cells = <1>;
363 #size-cells = <0>;
367 gpio-map-mask = <0xffffffe0 0xffffffc0>;
368 gpio-map-pass-thru = <0x1f 0x3f>;
369 gpio-map = <
376 #gpio-cells = <2>;
377 #address-cells = <1>;
378 #size-cells = <0>;
382 compatible = "ambiq,gpio-bank";
383 gpio-controller;
384 #gpio-cells = <2>;
391 compatible = "ambiq,gpio-bank";
392 gpio-controller;
393 #gpio-cells = <2>;
400 compatible = "ambiq,gpio-bank";
401 gpio-controller;
402 #gpio-cells = <2>;
409 compatible = "ambiq,gpio-bank";
410 gpio-controller;
411 #gpio-cells = <2>;
422 interrupts = <1 0>;
423 clock-frequency = <16>;
430 arm,num-irq-priority-bits = <3>;