Lines Matching +full:min +full:- +full:bus +full:- +full:freq
1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
5 #include <freq.h>
6 #include <zephyr/dt-bindings/adc/adc.h>
7 #include <zephyr/dt-bindings/i2c/i2c.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 uartclk: apb-pclk {
13 compatible = "fixed-clock";
14 clock-frequency = <DT_FREQ_M(24)>;
15 #clock-cells = <0>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,cortex-m4f";
26 cpu-power-states = <&idle &suspend_to_ram>;
27 #address-cells = <1>;
28 #size-cells = <1>;
31 compatible = "arm,armv7m-itm";
33 swo-ref-frequency = <DT_FREQ_M(6)>;
37 power-states {
39 compatible = "zephyr,power-state";
40 power-state-name = "suspend-to-idle";
45 min-residency-us = <100>;
46 exit-latency-us = <5>;
50 compatible = "zephyr,power-state";
51 power-state-name = "suspend-to-ram";
57 min-residency-us = <2000>;
58 exit-latency-us = <125>;
65 compatible = "zephyr,memory-region";
67 zephyr,memory-region = "ITCM";
72 compatible = "mmio-sram";
77 compatible = "zephyr,memory-region";
79 zephyr,memory-region = "XIP0";
83 compatible = "zephyr,memory-region";
85 zephyr,memory-region = "XIP1";
89 compatible = "zephyr,memory-region";
91 zephyr,memory-region = "XIP2";
95 compatible = "ambiq,apollo3p-blue", "ambiq,apollo3x", "simple-bus";
97 flash: flash-controller@c000 {
98 compatible = "ambiq,flash-controller";
101 #address-cells = <1>;
102 #size-cells = <1>;
106 compatible = "soc-nv-flash";
114 #pwrcfg-cells = <2>;
128 clock-frequency = <DT_FREQ_M(3)>;
129 clk-source = <2>;
137 clock-frequency = <DT_FREQ_M(3)>;
138 clk-source = <2>;
146 clock-frequency = <DT_FREQ_M(3)>;
147 clk-source = <2>;
155 clock-frequency = <DT_FREQ_M(3)>;
156 clk-source = <2>;
164 clock-frequency = <DT_FREQ_M(3)>;
165 clk-source = <2>;
173 clock-frequency = <DT_FREQ_M(3)>;
174 clk-source = <2>;
182 clock-frequency = <DT_FREQ_M(3)>;
183 clk-source = <2>;
191 clock-frequency = <DT_FREQ_M(3)>;
192 clk-source = <2>;
200 interrupt-names = "UART0";
204 zephyr,pm-device-runtime-auto;
211 interrupt-names = "UART1";
215 zephyr,pm-device-runtime-auto;
221 #address-cells = <1>;
222 #size-cells = <0>;
226 zephyr,pm-device-runtime-auto;
231 #address-cells = <1>;
232 #size-cells = <0>;
236 zephyr,pm-device-runtime-auto;
241 #address-cells = <1>;
242 #size-cells = <0>;
246 zephyr,pm-device-runtime-auto;
251 #address-cells = <1>;
252 #size-cells = <0>;
256 zephyr,pm-device-runtime-auto;
261 #address-cells = <1>;
262 #size-cells = <0>;
266 zephyr,pm-device-runtime-auto;
271 #address-cells = <1>;
272 #size-cells = <0>;
276 zephyr,pm-device-runtime-auto;
281 #address-cells = <1>;
282 #size-cells = <0>;
286 zephyr,pm-device-runtime-auto;
291 #address-cells = <1>;
292 #size-cells = <0>;
296 zephyr,pm-device-runtime-auto;
301 #address-cells = <1>;
302 #size-cells = <0>;
306 zephyr,pm-device-runtime-auto;
311 #address-cells = <1>;
312 #size-cells = <0>;
316 zephyr,pm-device-runtime-auto;
321 #address-cells = <1>;
322 #size-cells = <0>;
326 zephyr,pm-device-runtime-auto;
331 #address-cells = <1>;
332 #size-cells = <0>;
336 zephyr,pm-device-runtime-auto;
341 #address-cells = <1>;
342 #size-cells = <0>;
346 zephyr,pm-device-runtime-auto;
352 interrupt-names = "ADC";
353 channel-count = <10>;
354 internal-vref-mv = <1500>;
356 #io-channel-cells = <1>;
361 compatible = "ambiq,mspi-controller";
363 clock-frequency = <48000000>;
365 #address-cells = <1>;
366 #size-cells = <0>;
372 compatible = "ambiq,mspi-controller";
374 clock-frequency = <48000000>;
376 #address-cells = <1>;
377 #size-cells = <0>;
383 compatible = "ambiq,mspi-controller";
384 clock-frequency = <48000000>;
387 #address-cells = <1>;
388 #size-cells = <0>;
397 alarms-count = <1>;
402 compatible = "ambiq,spi-bleif";
405 #address-cells = <1>;
406 #size-cells = <0>;
410 bt_hci_apollo: bt-hci@0 {
411 compatible = "ambiq,bt-hci-spi";
412 spi-max-frequency = <DT_FREQ_M(6)>;
417 pinctrl: pin-controller@40010000 {
418 compatible = "ambiq,apollo3-pinctrl";
420 #address-cells = <1>;
421 #size-cells = <0>;
425 gpio-map-mask = <0xffffffe0 0xffffffc0>;
426 gpio-map-pass-thru = <0x1f 0x3f>;
427 gpio-map = <
433 #gpio-cells = <2>;
434 #address-cells = <1>;
435 #size-cells = <0>;
439 compatible = "ambiq,gpio-bank";
440 gpio-controller;
441 #gpio-cells = <2>;
448 compatible = "ambiq,gpio-bank";
449 gpio-controller;
450 #gpio-cells = <2>;
457 compatible = "ambiq,gpio-bank";
458 gpio-controller;
459 #gpio-cells = <2>;
472 clock-frequency = <16>;
479 arm,num-irq-priority-bits = <3>;