Lines Matching +full:exit +full:- +full:latency +full:- +full:us
1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
6 #include <zephyr/dt-bindings/adc/adc.h>
7 #include <zephyr/dt-bindings/i2c/i2c.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 uartclk: apb-pclk {
13 compatible = "fixed-clock";
14 clock-frequency = <DT_FREQ_M(24)>;
15 #clock-cells = <0>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,cortex-m4f";
26 cpu-power-states = <&idle &suspend_to_ram>;
27 #address-cells = <1>;
28 #size-cells = <1>;
31 compatible = "arm,armv7m-itm";
33 swo-ref-frequency = <DT_FREQ_M(6)>;
37 power-states {
39 compatible = "zephyr,power-state";
40 power-state-name = "suspend-to-idle";
42 * transition time are both lower than 1us, but considering
45 min-residency-us = <100>;
46 exit-latency-us = <5>;
50 compatible = "zephyr,power-state";
51 power-state-name = "suspend-to-ram";
53 * is the software overhead 1us and deepsleep_to_run transition
54 * time is about 25us,but considering the software overhead,
57 min-residency-us = <2000>;
58 exit-latency-us = <125>;
65 compatible = "zephyr,memory-region";
67 zephyr,memory-region = "ITCM";
72 compatible = "mmio-sram";
77 compatible = "zephyr,memory-region";
79 zephyr,memory-region = "XIP0";
83 compatible = "zephyr,memory-region";
85 zephyr,memory-region = "XIP1";
89 compatible = "zephyr,memory-region";
91 zephyr,memory-region = "XIP2";
95 compatible = "ambiq,apollo3p-blue", "ambiq,apollo3x", "simple-bus";
97 flash: flash-controller@c000 {
98 compatible = "ambiq,flash-controller";
101 #address-cells = <1>;
102 #size-cells = <1>;
106 compatible = "soc-nv-flash";
114 #pwrcfg-cells = <2>;
128 clock-frequency = <DT_FREQ_M(3)>;
129 clk-source = <2>;
137 clock-frequency = <DT_FREQ_M(3)>;
138 clk-source = <2>;
146 clock-frequency = <DT_FREQ_M(3)>;
147 clk-source = <2>;
155 clock-frequency = <DT_FREQ_M(3)>;
156 clk-source = <2>;
164 clock-frequency = <DT_FREQ_M(3)>;
165 clk-source = <2>;
173 clock-frequency = <DT_FREQ_M(3)>;
174 clk-source = <2>;
182 clock-frequency = <DT_FREQ_M(3)>;
183 clk-source = <2>;
191 clock-frequency = <DT_FREQ_M(3)>;
192 clk-source = <2>;
200 interrupt-names = "UART0";
204 zephyr,pm-device-runtime-auto;
211 interrupt-names = "UART1";
215 zephyr,pm-device-runtime-auto;
221 #address-cells = <1>;
222 #size-cells = <0>;
226 zephyr,pm-device-runtime-auto;
232 #address-cells = <1>;
233 #size-cells = <0>;
237 zephyr,pm-device-runtime-auto;
243 #address-cells = <1>;
244 #size-cells = <0>;
248 zephyr,pm-device-runtime-auto;
254 #address-cells = <1>;
255 #size-cells = <0>;
259 zephyr,pm-device-runtime-auto;
265 #address-cells = <1>;
266 #size-cells = <0>;
270 zephyr,pm-device-runtime-auto;
276 #address-cells = <1>;
277 #size-cells = <0>;
281 zephyr,pm-device-runtime-auto;
287 #address-cells = <1>;
288 #size-cells = <0>;
292 zephyr,pm-device-runtime-auto;
298 #address-cells = <1>;
299 #size-cells = <0>;
303 zephyr,pm-device-runtime-auto;
309 #address-cells = <1>;
310 #size-cells = <0>;
314 zephyr,pm-device-runtime-auto;
320 #address-cells = <1>;
321 #size-cells = <0>;
325 zephyr,pm-device-runtime-auto;
331 #address-cells = <1>;
332 #size-cells = <0>;
336 zephyr,pm-device-runtime-auto;
342 #address-cells = <1>;
343 #size-cells = <0>;
347 zephyr,pm-device-runtime-auto;
353 #address-cells = <1>;
354 #size-cells = <0>;
358 zephyr,pm-device-runtime-auto;
365 interrupt-names = "ADC";
366 channel-count = <10>;
367 internal-vref-mv = <1500>;
369 #io-channel-cells = <1>;
374 compatible = "ambiq,mspi-controller";
376 clock-frequency = <48000000>;
378 #address-cells = <1>;
379 #size-cells = <0>;
385 compatible = "ambiq,mspi-controller";
387 clock-frequency = <48000000>;
389 #address-cells = <1>;
390 #size-cells = <0>;
396 compatible = "ambiq,mspi-controller";
397 clock-frequency = <48000000>;
400 #address-cells = <1>;
401 #size-cells = <0>;
410 alarms-count = <1>;
415 compatible = "ambiq,spi-bleif";
418 #address-cells = <1>;
419 #size-cells = <0>;
423 bt_hci_apollo: bt-hci@0 {
424 compatible = "ambiq,bt-hci-spi";
425 spi-max-frequency = <DT_FREQ_M(6)>;
430 pinctrl: pin-controller@40010000 {
431 compatible = "ambiq,apollo3-pinctrl";
433 #address-cells = <1>;
434 #size-cells = <0>;
438 gpio-map-mask = <0xffffffe0 0xffffffc0>;
439 gpio-map-pass-thru = <0x1f 0x3f>;
440 gpio-map = <
446 #gpio-cells = <2>;
447 #address-cells = <1>;
448 #size-cells = <0>;
452 compatible = "ambiq,gpio-bank";
453 gpio-controller;
454 #gpio-cells = <2>;
461 compatible = "ambiq,gpio-bank";
462 gpio-controller;
463 #gpio-cells = <2>;
470 compatible = "ambiq,gpio-bank";
471 gpio-controller;
472 #gpio-cells = <2>;
485 clock-frequency = <16>;
492 arm,num-irq-priority-bits = <3>;