Lines Matching +full:mspi +full:- +full:max +full:- +full:frequency
1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
6 #include <zephyr/dt-bindings/adc/adc.h>
7 #include <zephyr/dt-bindings/i2c/i2c.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 uartclk: apb-pclk {
13 compatible = "fixed-clock";
14 clock-frequency = <DT_FREQ_M(24)>;
15 #clock-cells = <0>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,cortex-m4f";
26 cpu-power-states = <&idle &suspend_to_ram>;
27 #address-cells = <1>;
28 #size-cells = <1>;
31 compatible = "arm,armv7m-itm";
33 swo-ref-frequency = <DT_FREQ_M(6)>;
37 power-states {
39 compatible = "zephyr,power-state";
40 power-state-name = "suspend-to-idle";
45 min-residency-us = <100>;
46 exit-latency-us = <5>;
50 compatible = "zephyr,power-state";
51 power-state-name = "suspend-to-ram";
57 min-residency-us = <2000>;
58 exit-latency-us = <125>;
65 compatible = "zephyr,memory-region";
67 zephyr,memory-region = "ITCM";
72 compatible = "mmio-sram";
77 compatible = "ambiq,apollo3-blue", "ambiq,apollo3x", "simple-bus";
79 flash: flash-controller@0 {
80 compatible = "ambiq,flash-controller";
83 #address-cells = <1>;
84 #size-cells = <1>;
88 compatible = "soc-nv-flash";
96 #pwrcfg-cells = <2>;
110 clock-frequency = <DT_FREQ_M(3)>;
111 clk-source = <2>;
119 clock-frequency = <DT_FREQ_M(3)>;
120 clk-source = <2>;
128 clock-frequency = <DT_FREQ_M(3)>;
129 clk-source = <2>;
137 clock-frequency = <DT_FREQ_M(3)>;
138 clk-source = <2>;
146 clock-frequency = <DT_FREQ_M(3)>;
147 clk-source = <2>;
155 clock-frequency = <DT_FREQ_M(3)>;
156 clk-source = <2>;
164 clock-frequency = <DT_FREQ_M(3)>;
165 clk-source = <2>;
173 clock-frequency = <DT_FREQ_M(3)>;
174 clk-source = <2>;
182 interrupt-names = "UART0";
186 zephyr,pm-device-runtime-auto;
193 interrupt-names = "UART1";
197 zephyr,pm-device-runtime-auto;
203 #address-cells = <1>;
204 #size-cells = <0>;
208 zephyr,pm-device-runtime-auto;
213 #address-cells = <1>;
214 #size-cells = <0>;
218 zephyr,pm-device-runtime-auto;
223 #address-cells = <1>;
224 #size-cells = <0>;
228 zephyr,pm-device-runtime-auto;
233 #address-cells = <1>;
234 #size-cells = <0>;
238 zephyr,pm-device-runtime-auto;
243 #address-cells = <1>;
244 #size-cells = <0>;
248 zephyr,pm-device-runtime-auto;
253 #address-cells = <1>;
254 #size-cells = <0>;
258 zephyr,pm-device-runtime-auto;
263 #address-cells = <1>;
264 #size-cells = <0>;
268 zephyr,pm-device-runtime-auto;
273 #address-cells = <1>;
274 #size-cells = <0>;
278 zephyr,pm-device-runtime-auto;
283 #address-cells = <1>;
284 #size-cells = <0>;
288 zephyr,pm-device-runtime-auto;
293 #address-cells = <1>;
294 #size-cells = <0>;
298 zephyr,pm-device-runtime-auto;
303 #address-cells = <1>;
304 #size-cells = <0>;
308 zephyr,pm-device-runtime-auto;
313 #address-cells = <1>;
314 #size-cells = <0>;
318 zephyr,pm-device-runtime-auto;
323 #address-cells = <1>;
324 #size-cells = <0>;
328 zephyr,pm-device-runtime-auto;
334 interrupt-names = "ADC";
335 channel-count = <10>;
336 internal-vref-mv = <1500>;
338 #io-channel-cells = <1>;
343 compatible = "ambiq,mspi";
346 #address-cells = <1>;
347 #size-cells = <0>;
356 alarms-count = <1>;
361 compatible = "ambiq,spi-bleif";
364 #address-cells = <1>;
365 #size-cells = <0>;
369 bt_hci_apollo: bt-hci@0 {
370 compatible = "ambiq,bt-hci-spi";
371 spi-max-frequency = <DT_FREQ_M(6)>;
376 pinctrl: pin-controller@40010000 {
377 compatible = "ambiq,apollo3-pinctrl";
379 #address-cells = <1>;
380 #size-cells = <0>;
384 gpio-map-mask = <0xffffffe0 0xffffffc0>;
385 gpio-map-pass-thru = <0x1f 0x3f>;
386 gpio-map = <
391 #gpio-cells = <2>;
392 #address-cells = <1>;
393 #size-cells = <0>;
397 compatible = "ambiq,gpio-bank";
398 gpio-controller;
399 #gpio-cells = <2>;
406 compatible = "ambiq,gpio-bank";
407 gpio-controller;
408 #gpio-cells = <2>;
421 clock-frequency = <16>;
428 arm,num-irq-priority-bits = <3>;