Lines Matching +full:exit +full:- +full:latency +full:- +full:us
1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
6 #include <zephyr/dt-bindings/adc/adc.h>
7 #include <zephyr/dt-bindings/i2c/i2c.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 uartclk: apb-pclk {
13 compatible = "fixed-clock";
14 clock-frequency = <DT_FREQ_M(24)>;
15 #clock-cells = <0>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,cortex-m4f";
26 cpu-power-states = <&idle &suspend_to_ram>;
27 #address-cells = <1>;
28 #size-cells = <1>;
31 compatible = "arm,armv7m-itm";
33 swo-ref-frequency = <DT_FREQ_M(6)>;
37 power-states {
39 compatible = "zephyr,power-state";
40 power-state-name = "suspend-to-idle";
42 * transition time are both lower than 1us, but considering
45 min-residency-us = <100>;
46 exit-latency-us = <5>;
50 compatible = "zephyr,power-state";
51 power-state-name = "suspend-to-ram";
53 * the software overhead 1us and deepsleep_to_run transition time
54 * is about 25us,but considering the software overhead, we set
57 min-residency-us = <2000>;
58 exit-latency-us = <125>;
65 compatible = "zephyr,memory-region";
67 zephyr,memory-region = "ITCM";
72 compatible = "mmio-sram";
77 compatible = "ambiq,apollo3-blue", "ambiq,apollo3x", "simple-bus";
79 flash: flash-controller@0 {
80 compatible = "ambiq,flash-controller";
83 #address-cells = <1>;
84 #size-cells = <1>;
88 compatible = "soc-nv-flash";
96 #pwrcfg-cells = <2>;
110 clock-frequency = <DT_FREQ_M(3)>;
111 clk-source = <2>;
119 clock-frequency = <DT_FREQ_M(3)>;
120 clk-source = <2>;
128 clock-frequency = <DT_FREQ_M(3)>;
129 clk-source = <2>;
137 clock-frequency = <DT_FREQ_M(3)>;
138 clk-source = <2>;
146 clock-frequency = <DT_FREQ_M(3)>;
147 clk-source = <2>;
155 clock-frequency = <DT_FREQ_M(3)>;
156 clk-source = <2>;
164 clock-frequency = <DT_FREQ_M(3)>;
165 clk-source = <2>;
173 clock-frequency = <DT_FREQ_M(3)>;
174 clk-source = <2>;
182 interrupt-names = "UART0";
186 zephyr,pm-device-runtime-auto;
193 interrupt-names = "UART1";
197 zephyr,pm-device-runtime-auto;
203 #address-cells = <1>;
204 #size-cells = <0>;
208 zephyr,pm-device-runtime-auto;
214 #address-cells = <1>;
215 #size-cells = <0>;
219 zephyr,pm-device-runtime-auto;
225 #address-cells = <1>;
226 #size-cells = <0>;
230 zephyr,pm-device-runtime-auto;
236 #address-cells = <1>;
237 #size-cells = <0>;
241 zephyr,pm-device-runtime-auto;
247 #address-cells = <1>;
248 #size-cells = <0>;
252 zephyr,pm-device-runtime-auto;
258 #address-cells = <1>;
259 #size-cells = <0>;
263 zephyr,pm-device-runtime-auto;
269 #address-cells = <1>;
270 #size-cells = <0>;
274 zephyr,pm-device-runtime-auto;
280 #address-cells = <1>;
281 #size-cells = <0>;
285 zephyr,pm-device-runtime-auto;
291 #address-cells = <1>;
292 #size-cells = <0>;
296 zephyr,pm-device-runtime-auto;
302 #address-cells = <1>;
303 #size-cells = <0>;
307 zephyr,pm-device-runtime-auto;
313 #address-cells = <1>;
314 #size-cells = <0>;
318 zephyr,pm-device-runtime-auto;
324 #address-cells = <1>;
325 #size-cells = <0>;
329 zephyr,pm-device-runtime-auto;
335 #address-cells = <1>;
336 #size-cells = <0>;
340 zephyr,pm-device-runtime-auto;
347 interrupt-names = "ADC";
348 channel-count = <10>;
349 internal-vref-mv = <1500>;
351 #io-channel-cells = <1>;
359 #address-cells = <1>;
360 #size-cells = <0>;
369 alarms-count = <1>;
374 compatible = "ambiq,spi-bleif";
377 #address-cells = <1>;
378 #size-cells = <0>;
382 bt_hci_apollo: bt-hci@0 {
383 compatible = "ambiq,bt-hci-spi";
384 spi-max-frequency = <DT_FREQ_M(6)>;
389 pinctrl: pin-controller@40010000 {
390 compatible = "ambiq,apollo3-pinctrl";
392 #address-cells = <1>;
393 #size-cells = <0>;
397 gpio-map-mask = <0xffffffe0 0xffffffc0>;
398 gpio-map-pass-thru = <0x1f 0x3f>;
399 gpio-map = <
404 #gpio-cells = <2>;
405 #address-cells = <1>;
406 #size-cells = <0>;
410 compatible = "ambiq,gpio-bank";
411 gpio-controller;
412 #gpio-cells = <2>;
419 compatible = "ambiq,gpio-bank";
420 gpio-controller;
421 #gpio-cells = <2>;
434 clock-frequency = <16>;
441 arm,num-irq-priority-bits = <3>;