Lines Matching +full:w1 +full:- +full:gpio
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/dma/max78002_dma.h>
12 clock-frequency = <DT_FREQ_M(120)>;
16 clock-frequency = <DT_FREQ_K(30)>;
19 /delete-node/ &clk_erfo;
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <DT_FREQ_M(100)>;
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <DT_FREQ_M(25)>;
42 erase-block-size = <16384>;
48 gpio2: gpio@40080400 {
50 compatible = "adi,max32-gpio";
51 gpio-controller;
52 #gpio-cells = <2>;
58 gpio3: gpio@40080600 {
60 compatible = "adi,max32-gpio";
61 gpio-controller;
62 #gpio-cells = <2>;
69 compatible = "adi,max32-adc-sar", "adi,max32-adc";
70 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
71 clock-divider = <16>;
72 channel-count = <17>;
73 track-count = <4>;
74 idle-count = <0>;
75 vref-mv = <1250>;
83 compatible = "mmio-sram";
88 compatible = "mmio-sram";
93 compatible = "mmio-sram";
98 compatible = "mmio-sram";
103 compatible = "mmio-sram";
108 compatible = "mmio-sram";
113 compatible = "mmio-sram";
118 compatible = "adi,max32-uart";
121 clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
127 compatible = "adi,max32-spi";
129 #address-cells = <1>;
130 #size-cells = <0>;
137 compatible = "adi,max32-spi";
139 #address-cells = <1>;
140 #size-cells = <0>;
147 compatible = "adi,max32-dma";
151 dma-channels = <4>;
153 #dma-cells = <2>;
157 compatible = "adi,max32-watchdog";
161 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
166 compatible = "adi,max32-timer";
171 clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
174 compatible = "adi,max32-pwm";
176 #pwm-cells = <3>;
179 compatible = "adi,max32-counter";
185 compatible = "adi,max32-timer";
190 clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
193 compatible = "adi,max32-pwm";
195 #pwm-cells = <3>;
198 compatible = "adi,max32-counter";
203 w1: w1@4003d000 { label
204 compatible = "adi,max32-w1";