Lines Matching +full:one +full:- +full:timer +full:- +full:only

3  * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/drivers/timer/system_timer.h>
38  * This driver enables the Microchip XEC 32KHz based RTOS timer as the Zephyr
39  * system timer. It supports both legacy ("tickful") mode as well as
40  * TICKLESS_KERNEL. The XEC RTOS timer is a down counter with a fixed
42  * timer driver.
52  * program a periodic timer at this fast rate.
58 /* Mask off bits[31:28] of 32-bit count */
63 /* Adjust cycle count programmed into timer for HW restart latency */
67 /* max number of ticks we can load into the timer in one shot */
87  * One important invariant that must be observed: `total_cycles` + `cached_icr`
88  * is always an integral multiple of CYCLE_PER_TICK; this is, timer interrupts
89  * are only ever scheduled to occur at tick boundaries.
97  * Read the RTOS timer counter handling the case where the timer
99  * The RTOS timer hardware must synchronize the write to its control register
103  * was on. We detect the timer is in the load state by checking the read-only
105  * is 0 and the START bit is set then the timer has been started and is in the
126  * the tick announced as soon as possible, ideally no more than one tick
130  * RTMR counter register is read-only and is loaded from the preload
131  * register by a 0->1 transition of the control register start bit.
132  * Writing a new value to preload only takes effect once the count
147 		 * global objects safe from pre-emption?  in sys_clock_set_timeout()
157 		full_ticks = MAX_TICKS - 1;  in sys_clock_set_timeout()
159 		full_ticks = n - 1;  in sys_clock_set_timeout()
174 	temp += (cached_icr - ccr);  in sys_clock_set_timeout()
178 	partial_cycles = CYCLES_PER_TICK - (total_cycles % CYCLES_PER_TICK);  in sys_clock_set_timeout()
180 	/* adjust for up to one 32KHz cycle startup time */  in sys_clock_set_timeout()
183 		temp -= RTIMER_ADJUST_CYCLES;  in sys_clock_set_timeout()
207 	elapsed = (int32_t)total_cycles - (int32_t)last_announcement;  in sys_clock_elapsed()
209 		elapsed = -1 * elapsed;  in sys_clock_elapsed()
212 	ticks += cached_icr - ccr;  in sys_clock_elapsed()
232 	/* Restart the timer as early as possible to minimize drift... */  in mec5_ktimer_isr()
241 	/* handle wrap by using (power of 2) - 1 mask */  in mec5_ktimer_isr()
242 	ticks = total_cycles - last_announcement;  in mec5_ktimer_isr()
253 /* Non-tickless kernel build. */
262 	/* Restart the timer as early as possible to minimize drift... */  in mec5_ktimer_isr()
280  * Warning RTOS timer resolution is 30.5 us.
282  * 1. Kernel call to k_cycle_get_32() -> arch_k_cycle_get_32() -> here.
297 	ret = (total_cycles + (cached_icr - ccr)) & RTIMER_COUNT_MASK;  in sys_clock_cycle_get_32()
319  * 32-bit basic timer divided down to 1 MHz. Basic timer configured
320  * for count up, auto-reload, and no interrupt mode.
333 		if ((curr - start) >= usec_to_wait) {  in arch_busy_wait()
340  * Configure basic timer for 1 MHz (1 us tick) operation.