102 static inline uint32_t xlnx_quadspi_read32(const struct device *dev,  in xlnx_quadspi_read32()  function
155 		spicr = xlnx_quadspi_read32(dev, SPICR_OFFSET);  in xlnx_quadspi_configure()
220 	spisr = xlnx_quadspi_read32(dev, SPISR_OFFSET);  in xlnx_quadspi_configure()
251 			spicr = xlnx_quadspi_read32(dev, SPICR_OFFSET);  in xlnx_quadspi_start_tx()
263 		spicr = xlnx_quadspi_read32(dev, SPICR_OFFSET);  in xlnx_quadspi_start_tx()
296 			spisr = xlnx_quadspi_read32(dev, SPISR_OFFSET);  in xlnx_quadspi_start_tx()
306 					 xlnx_quadspi_read32(dev, SPI_TX_FIFO_OCR_OFFSET) - 1;  in xlnx_quadspi_start_tx()
311 	spisr = xlnx_quadspi_read32(dev, SPISR_OFFSET);  in xlnx_quadspi_start_tx()
317 		spicr = xlnx_quadspi_read32(dev, SPICR_OFFSET);  in xlnx_quadspi_start_tx()
342 	uint32_t spisr = xlnx_quadspi_read32(dev, SPISR_OFFSET);  in xlnx_quadspi_read_fifo()
345 		xlnx_quadspi_read32(dev, SPI_RX_FIFO_OCR_OFFSET) + 1 : 1;  in xlnx_quadspi_read_fifo()
349 		uint32_t drr = xlnx_quadspi_read32(dev, SPI_DRR_OFFSET);  in xlnx_quadspi_read_fifo()
370 			spisr = xlnx_quadspi_read32(dev, SPISR_OFFSET);  in xlnx_quadspi_read_fifo()
372 				xlnx_quadspi_read32(dev, SPI_RX_FIFO_OCR_OFFSET) + 1 : 1;  in xlnx_quadspi_read_fifo()
464 	spicr = xlnx_quadspi_read32(dev, SPICR_OFFSET);  in xlnx_quadspi_release()
479 	ipisr = xlnx_quadspi_read32(dev, IPISR_OFFSET);  in xlnx_quadspi_isr()
528 		 i < 10 && (xlnx_quadspi_read32(dev, SPISR_OFFSET) & SPISR_TX_EMPTY) == 0; i++) {  in xlnx_quadspi_startup_block_workaround()
531 	if ((xlnx_quadspi_read32(dev, SPISR_OFFSET) & SPISR_TX_EMPTY) == 0) {  in xlnx_quadspi_startup_block_workaround()
538 	while ((xlnx_quadspi_read32(dev, SPISR_OFFSET) & SPISR_RX_EMPTY) == 0) {  in xlnx_quadspi_startup_block_workaround()
539 		xlnx_quadspi_read32(dev, SPI_DRR_OFFSET);  in xlnx_quadspi_startup_block_workaround()