Lines Matching refs:SSP_WRITE_REG
236 #define SSP_WRITE_REG(reg, val) (*((volatile uint32_t *)reg) = val) macro
409 SSP_WRITE_REG(SSP_CPSR(cfg->reg), prescale); in spi_pl022_configure()
410 SSP_WRITE_REG(SSP_CR0(cfg->reg), cr0); in spi_pl022_configure()
411 SSP_WRITE_REG(SSP_CR1(cfg->reg), cr1); in spi_pl022_configure()
415 SSP_WRITE_REG(SSP_IMSC(cfg->reg), in spi_pl022_configure()
529 SSP_WRITE_REG(SSP_DMACR(cfg->reg), SSP_DMACR_MASK_RXDMAE | SSP_DMACR_MASK_TXDMAE); in spi_pl022_start_dma_transceive()
684 SSP_WRITE_REG(SSP_DR(cfg->reg), txrx); in spi_pl022_async_xfer()
709 SSP_WRITE_REG(SSP_ICR(cfg->reg), SSP_ICR_MASK_RORIC | SSP_ICR_MASK_RTIC); in spi_pl022_start_async_xfer()
722 SSP_WRITE_REG(SSP_IMSC(cfg->reg), 0); in spi_pl022_isr()
728 SSP_WRITE_REG(SSP_ICR(cfg->reg), SSP_ICR_MASK_RORIC | SSP_ICR_MASK_RTIC); in spi_pl022_isr()
765 SSP_WRITE_REG(SSP_DR(cfg->reg), txrx); in spi_pl022_xfer()